US3740668A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Variable duty-cycle and frequency oscillator circuit
Assignee: Motorola Solutions Inc
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Filing: 1971-09-20
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Granted: 1973-06-19
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Expires: 1991-09-20
Abstract
Abstract An oscillator circuit having a variable duty-cycle and frequency, both of which are determined by the amplitude of an input analog signal. The output of the invented circuit is a waveform having a fixed off-time and a variable on-time, the latter being inversely proportional to the amplitude of the input signal voltage level. The significant characteristic of the output waveform is that in each cycle the product of (i) the output voltage and (ii) the on-time is substantially constant. This output characteristic of the present invention makes it useful in a number of applications, one of which is as a voltage regulator. The invented circuit comprises, in part, (i) a pair of switches, typically transistors, which cyclically and alternately switch on and off, and (ii) a pair of charging capacitors which cyclically and alternately control the switching times of the switches. The fixed time constant with which one of the two charging capacitors is charged determines the fixed off-time of the circuit''s output waveform, while the variable charging rate of the second capacitor, a rate which is proportional to the input signal voltage, determines the variable on-time of the output waveform.
Inventors
- 👤 J Chopra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:29
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/145; H02M3/155; H02M3/156; H02M3/1563; H03; H03K; H03K7/00; H03K7/10
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
714 words
A variable duty-cycle and frequency oscillator circuit, adapted to receive an input signal at an input terminal and having an output terminal comprising: a. a DC electrical power source derived from said input signal by means of a power transistor having base, emitter and collector legs, said collector leg thereof being electrically coupled to said input terminal, said base leg thereof being electrically connected to a zener diode which is electrically coupled to said input terminal, and said emitter leg thereof being connected to an output point of said DC power source, whereby said power transistor is continually biased to a conducting state by said zener diode and said voltage on said output point is substantially constant; b. first and second transistors for switching, each of said transistors having base, collector and emitter legs, said collector legs of each being electrically coupled to said output point of said DC power source, said emitter legs of each being electrically connected to a circuit ground; c. first and second capacitors, each having first and second sides, said first and second sides of said first capacitor being electrically coupled to said base leg of said first switching transistor and said collector leg of said second switching transistor, respectively, and said first and second sides of said second capacitor being electrically coupled to said base leg of said second switching transistor and said collector leg of said first switching transistor, respectively; d. a source of current electrically coupled to said first side of said first capacitor, said current source comprising: i. a third transistor having base, collector and emitter legs, said emitter leg thereof being electrically coupled to said input terminal, said base leg thereof being electrically coupled to said output point of said DC power source and said collector leg thereof being electrically coupled to said first side of said first capacitor; ii. a pair of resistors serially disposed between said output point of said DC power source and said circuit ground, said resistors dividing the voltage of said DC power source; and iii. a fourth transistor having base, collector and emitter legs, said emitter leg thereof being electrically coupled to said output point of said DC power source, said base leg thereof being electrically coupled to a junction of said pair of resistors, and said collector leg thereof being electrically coupled to said first side of said first capacitor, whereby said third and fourth transistors are continually in a conducting state, said third transistor providing a collector current which is directly proportional to the amplitude of said input signal, and said fourth transistor providing a substantially constant collector current. e. a resistor electrically coupling said first side of said second capacitOr to said DC power source; and f. a fifth transistor for switching, said fifth transistor having base, collector and emitter legs, said collector leg thereof being electrically coupled to said input terminal, said emitter leg thereof being electrically coupled to said output terminal, and said base leg thereof being electrically coupled to said collector leg of said first transistor, whereby said first and second transistors each cyclically and alternately switching between conducting and non-conducting states, said first transistor being in a conducting state and said second transistor being in a non-conducting state for a fixed time interval during each cycle of operation of said circuit, said fixed time interval being the time required for said first side of said second capacitor to be charged by said DC power source to a bias voltage which causes said second transistor to conduct, and said second transistor being in a conducting state and said first transistor being in a non-conducting state for a variable time interval during each cycle of said operation, said variable time interval being the time required for said first side of said first capacitor to be charged by said current source to a bias voltage which causes said first transistor to conduct, said variable time interval being inversely proportional to the amplitude of said input signal, said cyclic switching of said first transistor causing said fifth transistor to be in a conducting state for said variable time interval and in a non-conducting state for said fixed interval, said input signal thereby appearing at said output terminal for said variable time interval of each cycle.
Claim 2
Dependent Claim
714 words
A variable duty-cycle and frequency oscillator circuit, adapted to receive an input signal at an input terminal and having an output terminal comprising: a. a DC electrical power source derived from said input signal by means of a power transistor having base, emitter and collector legs, said collector leg thereof being electrically coupled to said input terminal, said base leg thereof being electrically connected to a zener diode which is electrically coupled to said input terminal, and said emitter leg thereof being connected to an output point of said DC power source, whereby said power transistor is continually biased to a conducting state by said zener diode and said voltage on said output point is substantially constant; b. first and second transistors for switching, each of said transistors having base, collector and emitter legs, said collector legs of each being electrically coupled to said output point of said DC power source, said emitter legs of each being electrically connected to a circuit ground; c. first and second capacitors, each having first and second sides, said first and second sides of said first capacitor being electrically coupled to said base leg of said first switching transistor and said collector leg of said second switching transistor, respectively, and said first and second sides of said second capacitor being electrically coupled to said base leg of said second switching transistor and said collector leg of said first switching transistor, respectively; d. a source of current electrically coupled to said first side of said first capacitor, said current source comprising: i. a third transistor having base, collector and emitter legs, said emitter leg thereof being electrically coupled to said input terminal, said base leg thereof being electrically coupled to said output point of said DC power source and said collector leg thereof being electrically coupled to said first side of said first capacitor; ii. a pair of resistors serially disposed between said output point of said DC power source and said circuit ground, said resistors dividing the voltage of said DC power source; and iii. a fourth transistor having base, collector and emitter legs, said emitter leg thereof being electrically coupled to said output point of said DC power source, said base leg thereof being electrically coupled to a junction of said pair of resistors, and said collector leg thereof being electrically coupled to said first side of said first capacitor, whereby said third and fourth transistors are continually in a conducting state, said third transistor providing a collector current which is directly proportional to the amplitude of said input signal, and said fourth transistor providing a substantially constant collector current. e. a resistor electrically coupling said first side of said second capacitOr to said DC power source; and f. a fifth transistor for switching, said fifth transistor having base, collector and emitter legs, said collector leg thereof being electrically coupled to said input terminal, said emitter leg thereof being electrically coupled to said output terminal, and said base leg thereof being electrically coupled to said collector leg of said first transistor, whereby said first and second transistors each cyclically and alternately switching between conducting and non-conducting states, said first transistor being in a conducting state and said second transistor being in a non-conducting state for a fixed time interval during each cycle of operation of said circuit, said fixed time interval being the time required for said first side of said second capacitor to be charged by said DC power source to a bias voltage which causes said second transistor to conduct, and said second transistor being in a conducting state and said first transistor being in a non-conducting state for a variable time interval during each cycle of said operation, said variable time interval being the time required for said first side of said first capacitor to be charged by said current source to a bias voltage which causes said first transistor to conduct, said variable time interval being inversely proportional to the amplitude of said input signal, said cyclic switching of said first transistor causing said fifth transistor to be in a conducting state for said variable time interval and in a non-conducting state for said fixed interval, said input signal thereby appearing at said output terminal for said variable time interval of each cycle.
References Cited (Backward Citations)
US3253186A
Cited
FR1429616A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-18 | 1976-12-18 | 1977-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-18 | 1980-12-18 | 1981-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-18 | 1984-12-18 | 1985-06-19 | $7700.00 | Window Closed / Lapsed |