US3740576A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic logic interconnection
Assignee: Telefunken Electronic GmbH
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Filing: 1971-08-04
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Granted: 1973-06-19
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Expires: 1991-08-04
Abstract
Abstract A dynamic logic interconnection comprises a plurality of individual logic circuits connected in series, the individual logic circuits including a diode element in series with the controlled current path of an active circuit element, to which individual circuits single phase clock pulses are applied at the same time.
Inventors
- 👤 T Haraszti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
126 words
A dynamic logic interconnection comprising: a plurality of individual logic circuits connected in series, each of said individual logic circuits including a diode element and a field effect transistor which has a control electrode and first and second main electrodes forming a controlled current path of said transistor; said diode having one electrode connected to said first electrode; means connected for applying a single phase clock pulse to the other electrode of said diode of each of said logic circuits; means connected for applying input data to said control electrode; and, means connecting the connecting point between said diode and said first electrode of one of said individual circuits to the control electrode of the field effect transistor of the following one of said individual circuits.
Claim 2
Dependent Claim
126 words
A dynamic logic interconnection comprising: a plurality of individual logic circuits connected in series, each of said individual logic circuits including a diode element and a field effect transistor which has a control electrode and first and second main electrodes forming a controlled current path of said transistor; said diode having one electrode connected to said first electrode; means connected for applying a single phase clock pulse to the other electrode of said diode of each of said logic circuits; means connected for applying input data to said control electrode; and, means connecting the connecting point between said diode and said first electrode of one of said individual circuits to the control electrode of the field effect transistor of the following one of said individual circuits.
Claim 3
Dependent Claim
26 words
An interconnection as defined in claim 1, further comprising means for applying said single phase clock pulse to said second electrode of said field effect transistor.
Claim 4
Dependent Claim
20 words
An interconnection as defined in claim 1, further comprising means for grounding said second electrode of said field effect transistor.
Claim 5
Dependent Claim
23 words
A interconnection as defined in claim 1, wherein said field effect transistor comprises a MOS field effect transistor with an insulated control electrode.
Claim 6
Dependent Claim
59 words
An interconnection as defined in claim 1, wherein said individual circuits further comprise a further field effect transistor having its controlled current path connected in series with said field effect transistor and means are provided for applying separate input data to the control electrodes of said field effect transistors so that an AND or a NAND gate is produced.
Claim 7
Dependent Claim
60 words
An interconnection as defined in claim 1, wherein said individual circuits further comprise a further field effect transistor having its controlled current path in parallel with said controlled current path of said field effect transistor and means for applying separate input data to the control electrodes of said field effect transistors so that an OR or NOR gate is produced.
Claim 8
Dependent Claim
39 words
An interconnection as defined in claim 1, wherein the diode of each said individual circuit comprises a barrier layer junction between a substrate containing said individual circuit and said first and second electrodes respectively of said field effect transistor.
Claim 9
Dependent Claim
27 words
An interconnection as defined in claim 1, wherein said clock pulse applying means applies pulses which are shorter than pulses applied by said data input applying means.
Claim 10
Dependent Claim
43 words
An interconnection as defined in claim 1, wherein said individual circuits further comprise a capacitance for storing data and substantially consisting of a barrier layer capacitance of said field effect transistor, the output capacitance of the next said individual circuit and wire-to-ground capacitances.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-18 | 1976-12-18 | 1977-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-18 | 1980-12-18 | 1981-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-18 | 1984-12-18 | 1985-06-19 | $7700.00 | Window Closed / Lapsed |