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US3740537A Expired / Lapsed US ⏱️ 0.0 years remaining

Modified integrate and dump filter

Assignee: GTE Sylvania Inc
•
Filing: 1971-12-01
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Granted: 1973-06-19
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Expires: 1991-12-01
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Abstract

Abstract A modified integrate and dump (I&D) filter employs an input terminal coupled to a selector gate through a plurality of data paths, each path including bit delay elements of different values. The output connection of the selector gate is coupled to a digital integrate and dump filter. Each of the data paths is selectively energized to vary the bit delay of selected data samples to thereby weight the value of the selected samples before supplying the samples to the I&D filter.

Inventors

  • 👤 G Giles
  • 👤 J Lockitt

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 00:05
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 300 words
A nonrecursive filter to modify the characteristic of an integrate and dump filter comprising: variable delay means having an input terminal, an output terminal and a plurality of control terminals and being operative to delay a signal at its input terminal in selected increments of predetermined magnitude, the particular increment selected being determined by which of said control terminals is enabled; timing means having a plurality of output connections, each being coupled to a separate one of said control terminals and being operative to selectively generate enabling signals at its output connections to thereby select an increment of delay of particular magnitude in said variable delay means; and an integrate and dump filter means having an input connection coupled to the output connection of said variable delay means and an output connection and being operative to accumulate over a predetermined time interval the sum of the signals from said variable delay means; said variable delay means including a plurality of gates, each having a first input connection connected to a separate one of said plurality of control terminals, a second input connection, and an output connection coupled to said integrate and dump filter means, each of said plurality of gates being operative to pass a signal at its second input connection to said integrate and dump filter means upon the receipt of an enabling signal at its first input connection; and a plurality of delay paths, each path having an input connection connected to said input terminal of said variable delay means, and an output connection connected to a separate one of the second input connections of said plurality of gates and each path being operative to delay a signal at said input terminal an increment of predetermined magnitude before directing said signal to said integrate and dump filter means.
Claim 2
Dependent Claim 300 words
A nonrecursive filter to modify the characteristic of an integrate and dump filter comprising: variable delay means having an input terminal, an output terminal and a plurality of control terminals and being operative to delay a signal at its input terminal in selected increments of predetermined magnitude, the particular increment selected being determined by which of said control terminals is enabled; timing means having a plurality of output connections, each being coupled to a separate one of said control terminals and being operative to selectively generate enabling signals at its output connections to thereby select an increment of delay of particular magnitude in said variable delay means; and an integrate and dump filter means having an input connection coupled to the output connection of said variable delay means and an output connection and being operative to accumulate over a predetermined time interval the sum of the signals from said variable delay means; said variable delay means including a plurality of gates, each having a first input connection connected to a separate one of said plurality of control terminals, a second input connection, and an output connection coupled to said integrate and dump filter means, each of said plurality of gates being operative to pass a signal at its second input connection to said integrate and dump filter means upon the receipt of an enabling signal at its first input connection; and a plurality of delay paths, each path having an input connection connected to said input terminal of said variable delay means, and an output connection connected to a separate one of the second input connections of said plurality of gates and each path being operative to delay a signal at said input terminal an increment of predetermined magnitude before directing said signal to said integrate and dump filter means.
Claim 3
Dependent Claim 55 words
A nonrecursive filter according to claim 1 wherein the signal at said input terminal of said variable delay means includes a series of digital words representing a predetermined number of samples of a signal over a predetermined interval, each of said words containing a predetermined number of data bits representing the amplitude of one sample.
Claim 4
Dependent Claim 29 words
A nonrecursive filter according to claim 2 wherein said plurality of delay paths include bit delay elements operative to delay on a bit basis said series of digital words.
Claim 5
Dependent Claim 157 words
A nonrecursive filter according to claiM 2 wherein said integrate and dump filter means includes: a full adder circuit means having a first input connection connected to the output connection of said variable delay means, a second input connection, an output connection and a binary reference point associated therewith and being operative to add signals at its first and second input connections with respect to said binary reference point; and a shift register having an input connection connected to the output connection of said full adder circuit and an output connection connected to the second input connection of said full adder circuit and being operative to accumulate over a predetermined period and on a sample by sample basis the sum of the sum of the signals at the output connection of said full adder circuit and to transfer the accumulated sum on a sample by sample basis to the second input connection of said full adder circuit.

References Cited (Backward Citations)

US3521041A Cited
US3521042A Cited
US3522546A Cited
US3639739A Cited
US3659086A Cited
US3639848A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-06-18 1976-12-18 1977-06-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-06-18 1980-12-18 1981-06-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-06-18 1984-12-18 1985-06-19 $7700.00 Window Closed / Lapsed

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