Apparatus for producing coding pulse sequences

Claim 2

Apparatus for encoding messages comprising, means for generating a long period pulse sequence, means for generating a secret code, means for deriving from the long-period sequence and the secret code a code pulse sequence said deriving means including a plurality of shift registers, a plurality of logic circuits interconnecting said shift registers so that the binary value of each code pulse is defined by the binary values of a plurality of control pulses supplied to the shift registers earlier with respect to time, each code pulse remaining unaffected by that part of the control pulse sequence which occurs before the affected code pulse during an amount of time referred to as the transit time and subsequently referred as the total transit time, and means changing over the total transit time at intervals depending on the secrecy code and for a predetermined period of time from a larger to a smaller value.

Claim 3

Apparatus according to claim 1, in which at least one circuit part is so constructed that the mean value of its transit times, referred to hereinbelow as partial transit times, dOes not exceed a defined magnitude, said circuit part having a feedback path extending from its output to its input and in which the means for changing over the total transit time interrupts the feedback circuit at time intervals depending on the secrecy code and for a defined period of time, said periods of time being so defined that at least one of the feedback interruptions is longer than the simultaneously occurring part transit time within a defined period of time.

Claim 4

Apparatus according to claim 2, in which the mean value of the partial transit times and the mean value of the feedback interruption times are defined for each circuit part and for each associated feedback circuit so that the said two mean values coincide at least approximately.

Claim 5

Apparatus according to claim 2, in which the mean values of the partial transit times are identical for all circuit parts.

Claim 6

Apparatus according to claim 2, in which at least two units, each comprising one of the circuit parts defined as regards their partial transit times and one of the feedback circuits defined as regards their interruption periods, are connected in series.

Claim 7

Apparatus according to claim 2, in which at least two units, each comprising one of the circuit parts defined with regard to their partial transit times and one feedback circuit defined with regard to their interruption periods, are connected in parallel.

Claim 8

Apparatus according to claim 2, comprising means for controlling the periods during which the feedback is interrupted, said means being controlled by a control pulse sequence dependent on the secrecy code and comprising a code word detector and being adapted to interrupt the feedback for a defined period of time whenever said detector becomes operative, said code word detector triggering a counter which in turn interrupts the feedback for the duration of its counting period.

Claim 9

Apparatus according to claim 7, in which the code word detector is provided with a desired code word setting, said code word setting being controllable relative to the secrecy code.

Claim 10

Apparatus according to claim 1, comprising means for deriving the long-period pulse sequence from the date and time.

Claim 11

Apparatus according to claim 1, in which at least parts of the secrecy code are fed in, relative to the date and time.

Claim 12

Apparatus according to claim 1, in which the logic circuits are constructed as data flow control circuits which influence the data flow intermittently in at least one other shift register relative to the data flow in at least one other register.

Claim 13

Apparatus according to claim 1, in which at least one part of the shift registers is inter-connected to form a XY coordinate shift register system, but each shift register stage forms a junction of at least two chains (X,Y) at least part of the said chains being influenced by data flow control circuits.

Claim 14

Apparatus according to claim 12 comprising means for blocking the shifting cycles of all other cycles when the shifting cycles of one chain are switched on.

Claim 15

Apparatus according to claim 1, including an output stage adapted to form code words from the code pulse sequences supplied by the shift registers connected to the logic circuits, the length of the code words corresponding to the length of code words of clear-language data, which is to be encoded and also occurs in coded form, in which the output stage for each clear-language code word produces at least one complete encoded code word alphabet with a pseudo-statistic sequence of the individual alphabet code words and that the output stage is provided with a translator stage which substitutes one code word from one of the encoded code word alphabets for each clear-language code word.

Claim 16

Apparatus according to claim 14, in which the output and translator stage is provided with a ROM store (''''Read-Only-Memory'''') which contains all alphabet code words so that they can be sequentially called up through a parallel output, that each of the said parallEl outputs is connected to the first input of each of a signal comparator, that each of the second outputs of the aforementioned signal comparators are connected to a different point of a code pulse sequence output circuit, that each of the outputs of all signal comparators are connected to a separate stage of an intermediate store, that during each cycle of the output circuit the ROM store is completely interrogated at least once, that the ROM store, the signal comparators and the intermediate store are logically connected to each other and to a marker shift register, that all code words which have already occurred once during a defined period of time are cancelled in the intermediate store and that after the said period has elapsed the second inputs of the signal comparators are changed over from the code pulse sequence output circuit to the parallel outputs of the ROM store at least for the period of one interrogation cycle of the ROM store.