Electronic signal processing circuit

Claim 2

Electronic signal processing apparatus comprising: a first source of reference signals; a second source of signals having a characteristic which is to be sampled; a signal multiplier circuit having at least first and second input terminals coupled to said first and second sources, respectively, and a broad bandwidth load impedance coupled to an output terminal; a filter network; and sampling means operable between relatively low and high impedance states for alternately coupling said filter network to said output terminal for sampling said characteristic of said signals and for uncoupling said filter network from said output terminal so as to store information representative of said characteristics at said filter network.

Claim 3

Electronic signal processing apparatus according to claim 1 wherein: said filter network comprises the series combination of a resistance and a capacitance, and said load impedance comprises a resistance.

Claim 4

Electronic signal processing apparatus according to claim 2 wherein: said signal multiplier circuit comprises first, second and third pairs of differentially connected transistors, each transistor having base, emitter and collector electrodes, the base electrode of one transistor of said first pair providing said first input terminal, the emitter electrode of said transistors of said second pair being coupled together and to the collector electrode of said one transistor, the emitter electrodes of said transistors of said third pair being coupled together and to the collector electrode of the second transistor of said first pair, the base electrodes of first transistors of said second and third pairs being joined together to provide said second input terminals, the collector electrodes of a fist transistor of said second pair and a second transistor of said third pair being joined together and the collector electrodes of the second transistor of said second pair and the first transistor of said third pair being joined together, one of said sets of joined collectors of said second and third pairs being coupled to said output terminal.

Claim 5

Electronic signal processing apparatus according to claim 3 wherein: said sampling means comprises bidirectionally conductive means coupled to said filter network, and switching means coupled to said conductive means for rendering the latter bidirectionAlly conductive during each sampling interval and substantially non-conductive during a remaining portion of each operating cycle.

Claim 6

Electronic signal processing apparatus according to claim 3 wherein: said sampling means comprises first, second and third switching transistors each having base, emitter and collector electrodes, the base of said first switching transistor being coupled to said output terminal and the emitter thereof being coupled to said filter network, said second and third switching transistors being differentially coupled together with joined emitter electrodes, the collector of said second switching transistor being coupled to the base of said first switching transistor and the collector of said third switching transistor being coupled to the emitter of said first switching transistor, and a source of sampling signals coupled to at least one of the base electrodes of said second and third switching transistors for rendering said third switching transistor conductive and said second switching transistor non-conductive during each sampling interval and for rendering said second switching transistor conductive and said third switching transistor non-conductive during a remaining portion of each operating cycle.

Claim 7

Electronic signal processing apparatus according to claim 5 wherein: said filter resistance is coupled to the junction of the emitter of said first switching transistor and the collector of said third switching transistor.

Claim 8

Electronic signal processing apparatus according to claim 6 wherein: the base of said first switching transistor is coupled to said output terminal by means of a voltage follower transistor biased to conduction throughout each operating cycle.

Claim 9

Electronic signal processing apparatus according to claim 7 wherein: resistance means is coupled between said voltage follower transistor and said first switching transistor for conducting current to said second switching transistor during said remaining portion of each operating cycle.

Claim 10

Electronic signal processing apparatus according to claim 3 wherein: said first source of reference signals comprises means for generating a continuous wave at a frequency corresponding to the color subcarrier of a color television signal, and said second source of signals comprises a color television chrominance signal amplifier having an output signal including a periodically recurring color synchronizing burst component.

Claim 11

Electronic signal processing apparatus according to claim 9 wherein: said sampling means is operative to sample a characteristic of said color burst component and to store information representative of said characteristic at said filter capacitance.

Claim 12

Electronic signal processing apparatus according to claim 10 wherein: the sampled characteristic corresponds to the relative phase and frequency of said burst component compared to said continuous wave, and said sampling means includes an additional output terminal coupled to said filter resistance remote from said filter capacitance for providing pulses having a polarity representative of short term phase differences between said continuous wave and said burst component.

Claim 13

A sample and hold circuit comprising: a resistance-capacitance filter circuit; a source of signals which are to be sampled; switching means for intermittently coupling said source to said filter circuit, said switching means comprising a first transistor having an input electrode coupled to said source and an output electrode coupled to said filter circuit, differentially coupled second and third transistors having input electrodes, output electrodes coupled, respectively, to said input and output electrodes of said first transistor and common electrodes coupled to a current source, said switching means further comprising a source of sampling signals coupled to at least one of said input electrodes for rendering said third transistor conductive and said second tranSistor non-conductive during each sampling interval and for rendering said second transistor conductive and said third transistor non-conductive during a remaining portion of each operating cycle.

Claim 14

A sample and hold circuit comprising: a resistance-capacitance filter circuit; a source of signals which are to be sampled; switching means for intermittently coupling said source to said filter circuit, said switching means comprising a first transistor having an input electrode coupled to said source and an output electrode coupled to said filter circuit, differentially coupled second and third transistors having input electrodes, output electrodes coupled, respectively, to said input and output electrodes of said first transistor and common electrodes coupled to a current source, said switching means further comprising a source of sampling signals coupled to at least one of said input electrodes for rendering said third transistor conductive and said second tranSistor non-conductive during each sampling interval and for rendering said second transistor conductive and said third transistor non-conductive during a remaining portion of each operating cycle.

Claim 15

A sample and hold circuit according to claim 12 wherein: said input and output electrodes of said first transistor correspond, respectively, to base and emitter electrodes, said resistance of said filter circuit is coupled to said emitter electrode, and said first and third transistors are arranged for bidirectional current conduction through said resistance during said sampling intervals.

Claim 16

A sample and hold circuit according to claim 13 wherein: said input electrodes of said second and third transistors correspond to base electrodes, said common electrodes thereof correspond to emitter electrodes and said output electrodes thereof correspond to collector electrodes, and said first, second and third transistors are of like type conductivity.

Claim 17

A sample and hold circuit according to claim 14 wherein: said switching means further comprises a bias voltage source coupled to the base electrodes of one of said second and third transistors, said bias voltage being sufficient to maintain said one transistor conductive during the remaining portion of each operating cycle.

Claim 18

A sample and hold circuit according to claim 15 wherein: said first transistor is switched to conduction in response to said sampling signals during said sampling interval and is switched to non-conduction in response thereto during said remaining portion of each operating cycle.

Claim 19

A sample and hold circuit according to claim 16 wherein: said resistance comprises the sole current path from said switching means to said capacitance during said sampling interval and said current path is substantially open circuited during said remaining portion of each operating cycle.