Heterojunction information storage unit

Claim 2

An information storage unit comprising: a bistable semiconductor storage device having first, second and third regions of semiconductor material separated by two junctions, said first region and said third regions of a first types semiconductor material, said second region of a second type semiconductor material, terminal means on said first and third regions, said first type semiconductor material containing a high density of material imperfections, each of said junctions capable of exhibiting either a high impedance state or a low impedance state, said first region and said second region, said third region and said second region forming in series bistable switching elements in back to back relation, means to reverse the relative order of impedance states of said bistable switching elements, means to sense the relative order of the impedance states of said junctions.

Claim 3

The information storage unit of claim 1 wherein said means is to sense includes an energy source to apply electrical energy across the device terminals on said first and third regions.

Claim 4

The information storage unit of claim 2 wherein said means to sense includes means to determine whether or not a change in the order of impedance of the junctions is effected by said energy source.

Claim 5

The information storage unit of claim 3 wherein said means to sense includes a means to apply a subsequent energy pulse of opposite polarity to restore the original impedance state condition of said device after the original impedance state condition has been determined.

Claim 6

The information storage unit of claim 2 wherein said junctions of said device are of dissimilar area.

Claim 7

The information storage unit of claim 2 wherein said energy source generates a high frequency signal, and said means to sense determines the relative strength of the energy pulse conveyed through said device which is related to the relative capacitance of the junctions and the impedance states.

Claim 8

The information storage unit of claim 1 wherein said semiconductor device has two P-N heterojunctions in opposing relation.

Claim 9

An information storage unit having: at least one memory plane including pluralities of word lines and bit lines intersecting in a matrical manner to form a plurality of cross points, a storage cell located at each of said cross points, the inprovement comprising, said storage cells each comprised of a pair of bistable semiconductor heterojunctions in opposed series relation, each of said bistable heterojunctions formed by the interface between a first semiconductor material, and a second semiconductor material having a high density of imperfections which include deep energy traps existing at densities equal to or greater than the density of the doping of said sEcond material, said junctions each capable of alternately exhibiting either a stable high impedance state or a stable low impedance state, means to reverse the relative order of impedance states of said bistable semiconductor heterojunctions, sensing means to determine the relative order of impedance in the heterojunctions of said storage cell.

Claim 10

An information storage unit having: at least one memory plane including pluralities of word lines and bit lines intersecting in a matrical manner to form a plurality of cross points, a storage cell located at each of said cross points, the inprovement comprising, said storage cells each comprised of a pair of bistable semiconductor heterojunctions in opposed series relation, each of said bistable heterojunctions formed by the interface between a first semiconductor material, and a second semiconductor material having a high density of imperfections which include deep energy traps existing at densities equal to or greater than the density of the doping of said sEcond material, said junctions each capable of alternately exhibiting either a stable high impedance state or a stable low impedance state, means to reverse the relative order of impedance states of said bistable semiconductor heterojunctions, sensing means to determine the relative order of impedance in the heterojunctions of said storage cell.

Claim 11

The information storage unit of claim 8 wherein said sensing means includes energy means to selectively apply an energy pulse to said word lines of sufficient intensity to produce a change of impedances in said storage devices, and a means to detect a sharp current pulse in said bit lines indicative of a change of the order of impedances in said storage devices.

Claim 12

The information storage unit of claim 9 wherein said sensing means further includes a means to restore the impedance order by said energy means.

Claim 13

The information storage unit of claim 8 wherein said sensing means includes energy means to selectively apply coincidental pulses of differing polarity to said word lines and said bit lines to produce a change in the order of impedances in the junctions of said storage devices, and a means to detect a sharp current pulse in said bit lines indicative of a change in the order of impedances in said storage devices.

Claim 14

The information storage unit of claim 11 wherein said sensing means further includes a means to restore the impedance change produced by said energy means.

Claim 15

The information storage unit of claim 8 wherein said sensing means includes an energy means to selectively apply a high frequency signal to said word lines, said storage device having heterojunctions of differing area, a detection means responsive to a signal in said bit lines to determine the impedance state of the heterojunctions of said storage devices.