US3739199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Generator of a time interval as a multiple of a base period
Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
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Filing: 1971-12-16
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Granted: 1973-06-12
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Expires: 1991-12-16
Abstract
Abstract A standard time interval having a well-defined duration for use as a time measurement reference is delimited by two fronts separated by N periods of an oscillation having a preferably rectangular waveform and produced by a frequency standard oscillator. The generator comprises a trigger circuit which transmits clock pulses and synchronizes them with the fronts derived from the oscillator, a preset counting register operated by the clock pulses, two detectors for selecting the active clock-pulse fronts and each comprising a delay line, two amplifying circuits for collecting the active fronts and converting them into utilizable signals.
Inventors
- 👤 J Negrou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:02
CPC Classifications
G; G04; G04F; G04F5/00; G04G; G04G3/00; G04G3/02; H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03K5/14; H03K5/15; H03K5/15006
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
198 words
A generator for producing a standard time interval Tau NT delimited by two fronts separated by N periods of a periodic and preferably substantially rectangular oscillation having a period T and generated by a frequency standard oscillator, wherein said generator comprises in combination: a circuit for triggering and synchronizing with the fronts derived from the frequency standard oscillator, there being transmitted by said circuit only those pulses of said frequency standard oscillator which come after an order given by said trigger circuit as clock pulses, a counting register constituted by a count-down register which can be preset at the number N of periods to constitute the time standard, and the operation of which is initiated by the arrival of the clock pulses, a first detector for detecting the nth active clock-pulse front at the output of the synchronizing circuit, a second detector for detecting the (N + n)th active clock-pulse front, said detector being controlled by the counting register, two identical output amplifying circuits for collecting respectively and directly said nth and (N + n)th active clockpulse fronts which the first and second detectors have selected and allowed to pass in order to convert them into utilizable signals.
Claim 2
Dependent Claim
198 words
A generator for producing a standard time interval Tau NT delimited by two fronts separated by N periods of a periodic and preferably substantially rectangular oscillation having a period T and generated by a frequency standard oscillator, wherein said generator comprises in combination: a circuit for triggering and synchronizing with the fronts derived from the frequency standard oscillator, there being transmitted by said circuit only those pulses of said frequency standard oscillator which come after an order given by said trigger circuit as clock pulses, a counting register constituted by a count-down register which can be preset at the number N of periods to constitute the time standard, and the operation of which is initiated by the arrival of the clock pulses, a first detector for detecting the nth active clock-pulse front at the output of the synchronizing circuit, a second detector for detecting the (N + n)th active clock-pulse front, said detector being controlled by the counting register, two identical output amplifying circuits for collecting respectively and directly said nth and (N + n)th active clockpulse fronts which the first and second detectors have selected and allowed to pass in order to convert them into utilizable signals.
Claim 3
Dependent Claim
54 words
A generator according to claim 1, wherein the first detector for detecting the nth active clock-pulse front is constituted by a memory cell, a delay line and an AND-gate, the first permission input of said gate being coupled to the output of said delay line and the second input being coupled to the clock.
Claim 4
Dependent Claim
107 words
A generator according to claim 1, wherein said counting register which can be preset at the number N is a count-down register and said second detector for detecting the (N + n)th active clock-pulse front comprises: a detector for detecting the zero of the counting register constituted by AND-gates which receive the indications of state of all the dividers constituting the register, a second memory cell mounted immediately after said zero detector, a second delay line, and a second AND-gate of which the first permission input is coupled to the output of said second delay line and the second input of which is coupled to the clock.
Claim 5
Dependent Claim
99 words
A generator according to claim 1, wherein said circuit for triggering and synchronizing with the fronts derived from the frequency standard oscillator comprises a first synchronizing circuit constituted by a memory cell which receives the trigger pulse and is coupled to the permission input of an AND-gate of which the second input is coupled to the standard oscillator, and a second synchronizing circuit which is identical with the first and connected to the output of the first by means of a delay line, the output of the AND-gate of said second circuit being intended to generate said clock pulses.
Claim 6
Dependent Claim
101 words
A generator according to claim 2, wherein the adjustable time-delays d Tau 1 and d Tau 2 of the delay lines of the first and of the second detector respectively are chosen in such manner that the nth or the (N + n)th active clock-pulse front is the first to be detected by the corresponding detector and that the permission for opening each gate of the first and of the second detector respectively is given a sufficient length of time beforehand with substantially the same phase lead with respect to the nth or the (N + n)th active clock-pulse front respectively.
Claim 7
Dependent Claim
32 words
A generator according to claim 1, wherein each output amplifying circuit comprises a memory cell, a differentiating circuit, an amplifier proper, and a stage for injecting inverse currenT into a snap-off diode.
Claim 8
Dependent Claim
63 words
A generator according to claim 6, wherein the snap-off diode of each output amplifying circuit is under the control of an element for producing a current having a variable bias as a function of the temperature in order to maintain at identical values the times of transit of the signal between the input and the output of each of the two amplifying circuits.
Claim 9
Dependent Claim
31 words
A generator according to claim 7, wherein said element comprises at least one diode, an operational amplifier whose input is connected to the terminals of said diode and an emitter-follower amplifier.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-11 | 1976-12-11 | 1977-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-11 | 1980-12-11 | 1981-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-11 | 1984-12-11 | 1985-06-12 | $7700.00 | Window Closed / Lapsed |