Abstract Analog video signals which have a duty cycle which is substantially less than a total timing cycle are converted from analog to digital form in an analog to digital converter. These digital signals are fed to a time buffer where they are distributed over the entire timing cycle to lower their frequency so that the effective band width of such signals is substantially reduced. The time buffered signals are modulated onto an appropriate transmission carrier for transmission on a radio link or the like. These signals are received at the receiving station and appropriately processed to convert them back to their original analog form. In this manner, the band width of the transmission channel needed for transmitting the video signals may be substantially reduced.
A system for converting video signals to a form for transmission over a reduced bandwidth channel comprising: means for converting said signals from analog to digital form; means for converting the digital signals so derived from serial to parallel form; digital delay means for delaying preselected groups of said digital signals different predetermined amounts; and digital multiplexer switch and pulse stretcher means for receiving said delayed signals and a group of non-delayed signals directly from said converter means to place said signals in serial form distributed over a total time cycle.
Claim 2
Independent Claim
91 words
A system for converting video signals to a form for transmission over a reduced bandwidth channel comprising: means for converting said signals from analog to digital form; means for converting the digital signals so derived from serial to parallel form; digital delay means for delaying preselected groups of said digital signals different predetermined amounts; and digital multiplexer switch and pulse stretcher means for receiving said delayed signals and a group of non-delayed signals directly from said converter means to place said signals in serial form distributed over a total time cycle.
Claim 3
Dependent Claim
30 words
The system of claim 1 wherein said digital delay means comprises first and second digital delay lines for each delaying a separate group of said signals a different predetermined amount.
Claim 4
Dependent Claim
16 words
The device of claim 1 wherein said serial to parallel converter means comprises a shift register.
Claim 5
Dependent Claim
22 words
The device of claim 1 wherein said digital delay means comprises a shift register for delaying each of said groups of signals.
Claim 6
Dependent Claim
22 words
The device of claim 1 wherein said means for converting said video signals from analog to digital form comprises a delta modulator.
Claim 7
Independent Claim
126 words
A method for converting analog video signals from a form wherein they occupy a percentage of a total time cycle to a form wherein they occupy substantially the entire time cycle, comprising the steps of: converting said signals from analog to digital form so that they comprise a train of pulses representing the sign and slope of said analog video signals; converting said train of pulses to digital bits in parallel form; delaying selected groups of bits of said digital signal different predetermined amounts; and multiplexing and stretching said delayed groups of bits and a group of bits of said digital signal which have not been delayed onto a single output line in serial form, whereby said digital signals are distributed over the total time cycle.
Claim 8
Independent Claim
126 words
A method for converting analog video signals from a form wherein they occupy a percentage of a total time cycle to a form wherein they occupy substantially the entire time cycle, comprising the steps of: converting said signals from analog to digital form so that they comprise a train of pulses representing the sign and slope of said analog video signals; converting said train of pulses to digital bits in parallel form; delaying selected groups of bits of said digital signal different predetermined amounts; and multiplexing and stretching said delayed groups of bits and a group of bits of said digital signal which have not been delayed onto a single output line in serial form, whereby said digital signals are distributed over the total time cycle.