Bipolar conversion analog-to-digital converter

Claim 3

Apparatus in accordance with claim 1 wherein said sensing means includes means for storing the results of said polarity sensing at least until the end of the immediately following conversion cycle.

Claim 4

Apparatus in accordance with claim 2 which further includes logic means for providing a final said digital manifestation which is a function of the state of said storing means and the digital results of said immediately following conversion cycle.

Claim 5

Apparatus in accordance with claim 1 wherein said converter employs a counter circuit for developing said digital manifestation during a conversion cycle and wherein said correcting means includes means operable prior to commencement of the operation of said counter for developing said digital manifestation for introducing digital data to said counter so as to compensate for the magnitude of said reference signal.

Claim 6

Apparatus in accordance with claim 4 wherein said sensing means includes means for storing the polarity sensing results, said apparatus further including logic means coupled to the output of said counter and said storing means for providing a digital manifestation output at the end of a conversion cycle in the correct format as a function of the state of said storing means.

Claim 7

Apparatus in accordance with claim 1 wherein said converter employs a register or counter type circuit for presenting the digital manifestation results of each conversion cycle, said correcting means including subtractive logic means for reducing the content of said register at the end of each conversion cycle by an amount digitally correlated to the magnitude of said reference signal.

Claim 8

Apparatus in accordance with claim 6 wherein said sensing means includes means for storing the polarity sensing results, said apparatus further including interpreting logic means coupled to the output of said register as compensated by said subtractive logic means for providing a digital manifestation output at the end of each conversion cycle in the correct format indicated by the state of said storing means.

Claim 9

Apparatus in accordance with claim 1 wherein said inverting means includes a unity gain amplifier coupled to receive said unknown analog signals.

Claim 10

In a multi-ramp analog to digital converter employing an integrator, at least one reference signal and a counter wherein a conversion cycle is effected by integrating the unknown analog input for a fixed period and thereafter switching to integrate said reference signal or signals while incrementing said counter so as to reflect the time required to return said integrator output to the same level as at the start of said fixed period, an improvement comprising comparator means for receiving the unknown analog input and generating an output signal indicating the polarity thereof, means operable prior to commencement of a said conversion cycle for storing said comparator means output for at least one succeeding conversion cycle, unity gain inverting means, connected for receiving said unknown analog, means operable during said fixed period in response to said storing means for either directly coupling the unknown analog to said integrator input or coupling the output of said inverter means thereto, a source of offset voltage having a magnitude at least sufficiently large as the level at which said comparator means will operate substantially free from error, MEANS for combining said offset voltage with the input of said integrator so that said integrator will integrate the differential between said offset voltage and any other signal coupled to the input thereof, means operable at the conclusion of said fixed period for presetting said counter to a count for compensating for said offset voltage, and logic circuit means for providing readout signals from said counter at the end of a conversion cycle in direct or complementary form as indicated by the state of said storing means.

Claim 11

In a multi-ramp analog to digital converter employing an integrator, at least one reference signal and a counter wherein a conversion cycle is effected by integrating the unknown analog input for a fixed period and thereafter switching to integrate said reference signal or signals while incrementing said counter so as to reflect the time required to return said integrator output to the same level as at the start of said fixed period, an improvement comprising comparator means for receiving the unknown analog input and generating an output signal indicating the polarity thereof, means operable prior to commencement of a said conversion cycle for storing said comparator means output for at least one succeeding conversion cycle, unity gain inverting means, connected for receiving said unknown analog, means operable during said fixed period in response to said storing means for either directly coupling the unknown analog to said integrator input or coupling the output of said inverter means thereto, a source of offset voltage having a magnitude at least sufficiently large as the level at which said comparator means will operate substantially free from error, MEANS for combining said offset voltage with the input of said integrator so that said integrator will integrate the differential between said offset voltage and any other signal coupled to the input thereof, means operable at the conclusion of said fixed period for presetting said counter to a count for compensating for said offset voltage, and logic circuit means for providing readout signals from said counter at the end of a conversion cycle in direct or complementary form as indicated by the state of said storing means.