Stack register renamer

Claim 2

A stack memory system for storing a logical stack of information comprising: a plurality of stack registers for storing logical stack information, each stack register having an information input and output; a first data register for storing a number representative of the number of stack registers that contain logical stack information; a second data register for storing a naming state number representing the logical order of the information stored in the stack registers, the number of naming states being equal to the number of stack registers; first logic means having a plurality of ordered access input means, the first logic means being connected to the second data register and to each stack register for connecting an ordered access input means to each of the stack registers in response to the naming state number stored in the second data register for enabling stack register access via said information input and output in response to control signals on the ordered access input means, a different ordered access input means being connected to a given stack register for each of said naming state numbers and a change of one in said naming state number effecting the connection of the adjacent ordered access input means to a given stack register, the relative order between stack registers being preserved; and second logic means connected to the first and second data registers for stepping the first and second data registers in response to the addition and removal of information from the stack registers.

Claim 3

A stack memory system as in claim 1 wherein: each stack register has a store input for causing the stack register to store information present on the information input and a read input for causing information stored in the stack register to appear on the information output; the first logic means includes a read logic means for enabling the stack registers to output information on the information output and a store logic means for enabling the stack registers to store information present on the information input; a portion of the ordered access input means is ordered read inputs connected to the read logic means; another portion of the ordered access input means is ordered store inputs connected to the store logic means; the read logic means connect the ordered read inputs to the stack register read inputs in response to the naming state number stored in the second data register; and the store logic means connect the ordered store inputs to the stack register store inputs in response to the naming state number stored in the second data register.

Claim 4

A stack memory system as in claim 2 wherein: the number of ordered read inputs and of ordered store inputs is equal to the number of stack registers, N; and the read logic means and the store logic means each include an N bit multiplexer for each stack register.

Claim 5

A stack memory system as in claim 3 including third logic means for adding information to the top of the logical stack of information in response to a first external signal and for removing information from the top of said stack in response to a second external signal, the third logic means being connected to the first and second data registers, and to the last of the ordered store inputs, the first external signal causing the third logic means to: place a control signal on the last ordered store input to cause information to be stored in the stack register connected to that last ordered store input; decoder step the first data register to indicate an increase in the number of stack registers containing stack information; and step the second data register to change the connection of the stack register just accessed from the last to the first ordered store input; and the second external signal causing the third logic means to: step the first data register to indicate a decrease in the number of stack registers containing stack information; and step the second data register to connect the last ordered store and read inputs to the stack register previously connected to the first ordered store and read inputs.

Claim 6

A stack memory system as in claim 1 including: a read-write memory having a plurality of addressable locations for storing at least a portion of the logical stack of information; a third data register for storing the address of the top piece of information in the stack contained in the read-write memory; fourth logic means connected to the stack registers, to the first, second, and third data registers, and to the first and second logic means for transferring logical stack information from the read-write memory to a stack register in response to a first external signal and for transferring logical stack information from a stack register to the read-write memory in response to a second external signal.

Claim 7

A stack memory system as in claim 5 wherein: each stack register has a store input for causing the stack register to store information present on the information input and a read input for causing information stored in the stack register to appear on the information output; the first logic means includes a read logic means for enabling the stack registers to output information on the information output and a store logic means for enabling the stack registers to store information present on the information input; a portion of the ordered access input means is ordered read inputs connected to the read logic means; another portion of the ordered access input means is ordered store inputs connected to the store logic means; the read logic means connect the ordered read inputs to the stack register read inputs in response to the naming state number stored in the second data register; and the store logic means connect the ordered store inputs to the stack register store inputs in response to the naming state number stored in the second data register.

Claim 8

A stack memory system as in claim 6 wherein: the number of ordered read inputs and of ordered store inputs is equal to the number of stack registers, N; and the read logic means and the store logic means each include an N bit multiplexer for each stack register.

Claim 9

A stack memory system as in claim 7 including third logic means for adding information to the top of the logical stack of information in response to a first external signal and for removing information from the top of said stack in response to a second external signal, the third logic means being connected to the first and second data registers, to the information input and output and to the last of the ordered store inputs, the first external signal causing the third logic means to: place a control signal on the last ordered store input to cause information to be stored in the stack register connected to that last ordered store input; step the first data register to indicate an increase in the number of stack registers containing stack information; and step the second data register to change the connection of the stack register just accessed from the last to the first ordered store input; and the second external signal causing the third logic means to: step the first data register to indicate a decrease in the number of stack registers containing stack information; and step the second data register to connect the last ordered store and read inputs to the stack register previously connected to the first ordered store and read inputs.

Claim 10

A stack memory system as in claim 8 wherein the fourth logic means includes: an adder having inputs connected to the first and second data registers and having an output; a multiplexer having inputs connected to the output of the adder, and to the second data register, and having an output connected to the read logic means and store logic means; a logic element connected to the multiplexer for signalling the multiplexer to connect the adder to the read logic means and the store logic means for establishing a temporary naming state number in response to the first or second external signal whereby in response to the first external signal the top piece of information in the read-write memory is transferred to the stack register connected to the first ordered store input, the first data register is stepped to indicate an increase in the number of stack registers containing stack information, and the third data register is stepped to indicate the removal of a piece of information from the top of the stack of information in the read-write memory; and in response to the second external signal the information in the stack register connected to the last ordered read input is transferred to the location in the read-write memory immediately above the top piece of information in the logical stack therein, the first data register is stepped to indicate a decrease in the number of stack registers containing stack information, and the third data register is stepped to indicate the addition of a piece of information to the top of the stack in the read-write memory.

Claim 11

A stack memory system as in claim 9 including a fourth data register for storing a computed number; and adder means having inputs connected to the second and fourth data registers for adding said computed number to the number in the second data register and having an output connected to the read logic means and the store logic means in response to an external signal.