US3737870A
Expired / Lapsed
US
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Status switching arrangement
Assignee: International Business Machines Corp
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Filing: 1972-04-24
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Granted: 1973-06-05
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Expires: 1992-04-24
Abstract
Abstract There is disclosed a switching arrangement for effecting storage module reconfiguration in a data processing system wherein the memory comprises a quantity q of operating n-bit/BSM''s (basic storage modules) and a quantity s of spare n-bit/BSM''s. The arrangement comprises an input status register means which in turn comprises an input status register associated with each of the BSM''s respectively, which control an input reconfiguration network, and an output status register means which comprises an output status register respectively associated with each of the BSM''s, which control an output reconfiguration network. The input and output status registers and the input and output reconfiguration networks are of like structures, respectively. Initially, in normal operation, the operating BSM''s are connected to respective bit positions and all of the input and output status registers assume a chosen initial state. Initially, upon the ascertaining from a diagnosis, for example, that one of the operating BSM''s has failed, the input status register with which the failed BSM is associated is forced to a parity state opposite from the normal operating parity state, and all of the input status registers succedding in designated numerical value are switched to a next state. This causes the failed BSM to be disconnected from the input; the input originally connected to the failed BSM is connected to the BSM of succeeding higher value, the next higher input connected to the next BSM and so on until the last input is connected to the first pare BSM. At this point, all of the contents of the memory, i.e., the initially operating BSM''s, are passed through the output reconfiguration network under the control of the output status registers (which is not yet altered) and through a correction circuit wherein there is provided means for applying an error correction code. The memory contents are then passed from the correction circuit back into the present operating BSM''s through the input reconfiguration network under the control of the input status registers. Thereafter, the contents of the output status registers are then brought into conformity with the present contents of the input status registers whereupon normal operation can resume. The arrangement permits as many changes in the contents, i.e., states of the status registers after their initial states as there are spare BSMM''s in the memory organization, the contents of status registers of operating BSM''s which succeed a failed BSM being switched to a next state. Suitably, an operating parity state of a status register is of even parity and, when its associated BSM fails, its state is forced to an odd parity. An algorithm is presented for diagnosing as a failed BSM which is based upon the criterion of the ascertaining of a bit position which has undergone corrections most frequently over a chosen period of time. The switching arrangement also contemplates a basic storage module reconfiguration in the case of a status register failure in which situation, similar events ensue in the arrangements operation as would have occurred has a BSM failed.
Inventors
- 👤 W Carter
- 👤 E Hsieh
- 👤 A Wadia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:20
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
483 words
In a data processing system which comprises information containing components, means for transferring contents between said components, means for changing the contents of said components, means for controlling the sequence of operations in said system, a memory organization comprising a quantity q of operating basic storage modules and a quantity s of spare basic storage modules, and means for detecting failures in said components and said memory organization, a control apparatus for said memory organization comprising: input status register means comprising a quantity q+s of input status registers, each of said input status registers being capable of assuming at least s+1 successively occurring states in said predetermined sequence in a chosen normally operating parity, and a parity state opposite to said chosen parity; an input reconfiguration network; means for associating each of said input status registers with a respective one of said basic storage modules; output status register means comprising a quantity q+s of output status registers, each of said outpUt status registers being capable of assuming at least said s+1 successively occurring states in a chosen normally operating parity, and a parity state opposite to said chosen parity; an output reconfiguration network; means for associating each of said output status registers with a respective one of said basic storage modules; said input and output status registers associated respectively with each of said q+s quantity of basic storage modules initially being in a first of said successive states in said chosen parity; means for connecting said operating basic storage modules to respective bit positions through said reconfiguration networks; correction means for receiving the contents of said basic storage modules through said output reconfiguration network under the control of said output status register means; and means for providing the output of said correction means to said basic storage modules through said input reconfiguration network under the control of said input status register means; whereby, upon the detection by said failure detection means of a failure in one of said basic storage modules or in one of said status registers, the failed basic storage module or the basic storage module associated with the failed status register is caused to be switched out as an operating basic storage module, a spare basic storage module is switched in, the states of the input status registers associated with the remaining operating modules of a higher order than the failed basic storage module and said remaining spare basic storage modules are changed to the next state, of said predetermind state sequence, the contents of said basic storage modules are passed through said correction means and back into said basic storage modules, and contents of said output status registers are conformed with the contents of said input status registers, thereby enabling the resumption of normal operation by said memory organization, said organization being capable of operating with up to a total of s basic storage module and status register failures.
Claim 2
Dependent Claim
483 words
In a data processing system which comprises information containing components, means for transferring contents between said components, means for changing the contents of said components, means for controlling the sequence of operations in said system, a memory organization comprising a quantity q of operating basic storage modules and a quantity s of spare basic storage modules, and means for detecting failures in said components and said memory organization, a control apparatus for said memory organization comprising: input status register means comprising a quantity q+s of input status registers, each of said input status registers being capable of assuming at least s+1 successively occurring states in said predetermined sequence in a chosen normally operating parity, and a parity state opposite to said chosen parity; an input reconfiguration network; means for associating each of said input status registers with a respective one of said basic storage modules; output status register means comprising a quantity q+s of output status registers, each of said outpUt status registers being capable of assuming at least said s+1 successively occurring states in a chosen normally operating parity, and a parity state opposite to said chosen parity; an output reconfiguration network; means for associating each of said output status registers with a respective one of said basic storage modules; said input and output status registers associated respectively with each of said q+s quantity of basic storage modules initially being in a first of said successive states in said chosen parity; means for connecting said operating basic storage modules to respective bit positions through said reconfiguration networks; correction means for receiving the contents of said basic storage modules through said output reconfiguration network under the control of said output status register means; and means for providing the output of said correction means to said basic storage modules through said input reconfiguration network under the control of said input status register means; whereby, upon the detection by said failure detection means of a failure in one of said basic storage modules or in one of said status registers, the failed basic storage module or the basic storage module associated with the failed status register is caused to be switched out as an operating basic storage module, a spare basic storage module is switched in, the states of the input status registers associated with the remaining operating modules of a higher order than the failed basic storage module and said remaining spare basic storage modules are changed to the next state, of said predetermind state sequence, the contents of said basic storage modules are passed through said correction means and back into said basic storage modules, and contents of said output status registers are conformed with the contents of said input status registers, thereby enabling the resumption of normal operation by said memory organization, said organization being capable of operating with up to a total of s basic storage module and status register failures.
Claim 3
Dependent Claim
61 words
In a data processing system as defined in claim 1 wherein: upon the detection of a failed BSM, the input status register associated with said failed BSM is changed to said parity state opposite to said chosen parity prior to the passing of the contents of said basic storage modules through said correction means and back into said basic storage modules.
Claim 4
Dependent Claim
109 words
In a data processing system as defined in claim 1 wherein said basic storage modules and the status registers associated therewith are designated in ordered numerical value and wherein status registers of a particular numerical designation are associated with the basic storage module having the same numerical designation; and further including an ordered list of failed basic storage modules for including therein the information of a switched out and unavailable basic storage module, whereby, upon the switching out of an operating basic storage module, a spare basic storage module is switched into operation, and said basic storage module bit positions connections are reconfigured in accordance with said reconfiguration networks.
Claim 5
Dependent Claim
186 words
In a data processing system as defined in claim 3 wherein said operating basic storage modules and the status registers associated therewith have corresponding first to qth numerically ordered designations, wherein said spare basic storage modules and the status registers associated therewith have (qth + first) to (q + sth) numerically ordered designations, hwerein said first to qth basic storage modules are connected to correspondingly numerically ordered bit positions, wherein said successively occurring states occurring in said chosen parity are numerically ordered from first to (s + 1)th, wherein initially said status registers associated with all of said q + s basic storage modules assume the first of said successively occurring stAtes, whereby, upon the switching out of a basic storage module, there is switched in the next available spare basic storage module according to said order and the states of the status registers associated with the remaining operating basic storage modules whose numerical designations follow the numerical designation of said switched-out basic storage module in said order and said remaining spare basic storage modules are changed to the next state in said predetermined state sequence.
Claim 6
Independent Claim
501 words
A system for effecting storage module reconfiguration in the memory of a data processing system wherein said memory comprises a quantity q of operating n-bit BSM''s and a quantity s of spare n-bit BSM''s, said system comprising: input status register means comprising a q + s quantity of input status registers, each of said input status registers being capable of successively assuming first to (s + 1)th states and of a chosen parity and of assuming a parity opposite to said chosen parity; output status register means comprising a q + s quantity of output status registers, each of said output status registers being capable of successively assuming a first to (s + 1)th states and of said chosen parity, and of assuming said parity opposite to said chosen parity; an input reconfiguration network; means for correcting said operating BSM''s to respective numerically ordered bit positions through said input and output configuration networks, respectively; means for associating each of said input status registers, with each of said BSM''s respectively, said input status registers associated with said q + s BSM''s initially being in said first of said successive states; means for associating each of said output status registers with each of said BSM''s respectively, said output status registers associated with said q + s BSM''s initially being in said first of said successive states, BSM and status register failure response means respnsive to the ascertaining that one of said BSM''s of status register has failed, comprising: means for switching the state of the input status register associated with a failed BSM to said opposite parity state; means for switching out failed BSM or a BSM associated with a failed status register; means for switching the state of the input status registers associated with the remaining operating BSM''s which are connected to bit positions of numerical value further in said order than the values of the bit positions to which the switched-out BSM was connected and the remaining spare BSM''s to the next of said successive states, and means for connecting a spare BSM into the system, in response to the switching-out of an operating BSM ; error correction means; means for applying the contents of the BSM''s through said output configuration network under the control of said output status registers to said error correction means to correct said contents; means for providing said corrected contents to said BSM''s through said input reconfiguration network under the control of said input status registers; and means for respectively conforming the contents of said output status registers with the contents of said input status registers to enable the resumption of normal operation, the operation of said BSM failure responsive means causing the switching out of each successively occurring failed BSM or BSM associated with a failed status register as each failure is detected, the addition of the appropriate spare BSM completing the set of operating BSM''s until no more spare BSM''s remain, and the concomitant successive appropriate switching of the states of said status registers.
Claim 7
Independent Claim
501 words
A system for effecting storage module reconfiguration in the memory of a data processing system wherein said memory comprises a quantity q of operating n-bit BSM''s and a quantity s of spare n-bit BSM''s, said system comprising: input status register means comprising a q + s quantity of input status registers, each of said input status registers being capable of successively assuming first to (s + 1)th states and of a chosen parity and of assuming a parity opposite to said chosen parity; output status register means comprising a q + s quantity of output status registers, each of said output status registers being capable of successively assuming a first to (s + 1)th states and of said chosen parity, and of assuming said parity opposite to said chosen parity; an input reconfiguration network; means for correcting said operating BSM''s to respective numerically ordered bit positions through said input and output configuration networks, respectively; means for associating each of said input status registers, with each of said BSM''s respectively, said input status registers associated with said q + s BSM''s initially being in said first of said successive states; means for associating each of said output status registers with each of said BSM''s respectively, said output status registers associated with said q + s BSM''s initially being in said first of said successive states, BSM and status register failure response means respnsive to the ascertaining that one of said BSM''s of status register has failed, comprising: means for switching the state of the input status register associated with a failed BSM to said opposite parity state; means for switching out failed BSM or a BSM associated with a failed status register; means for switching the state of the input status registers associated with the remaining operating BSM''s which are connected to bit positions of numerical value further in said order than the values of the bit positions to which the switched-out BSM was connected and the remaining spare BSM''s to the next of said successive states, and means for connecting a spare BSM into the system, in response to the switching-out of an operating BSM ; error correction means; means for applying the contents of the BSM''s through said output configuration network under the control of said output status registers to said error correction means to correct said contents; means for providing said corrected contents to said BSM''s through said input reconfiguration network under the control of said input status registers; and means for respectively conforming the contents of said output status registers with the contents of said input status registers to enable the resumption of normal operation, the operation of said BSM failure responsive means causing the switching out of each successively occurring failed BSM or BSM associated with a failed status register as each failure is detected, the addition of the appropriate spare BSM completing the set of operating BSM''s until no more spare BSM''s remain, and the concomitant successive appropriate switching of the states of said status registers.
Claim 8
Dependent Claim
61 words
A system as defined in claim 5 wherein said input and output status registers are of equal bit length, wherein each input status register corresponds to one of said output status Registers, each of said last-named registers being associated with the same BSM and wherein each of said input and output status registers has a length of 1+ log2 (s+1) bits.
Claim 9
Dependent Claim
51 words
A system as defined in claim 6 wherein said BSM''s said input registers and said output registers are ordered by numerical value, said input and output status registers being associated with BSM''s of the same numerical value, respectively, and wherein there is further included; an ordered list of said failed BSM''s.
Claim 10
Dependent Claim
37 words
A system as defined in claim 7 wherein said BSM failure response means further includes means responsive to said failed BSM list for ascertaining the next spare BSM available to be switched in as an operating BSM.
Claim 11
Dependent Claim
44 words
A system as defined in claim 8 wherein the contents of the registers of said operating and available spare BSM''s are in an even parity state and wherein the contents of the status registers associated with failed BSM''s are in an odd parity state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-04 | 1976-12-04 | 1977-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-04 | 1980-12-04 | 1981-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-04 | 1984-12-04 | 1985-06-05 | $7700.00 | Window Closed / Lapsed |