US3737869A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electric control distributor
Assignee: International Standard Electric Corp
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Filing: 1972-02-11
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Granted: 1973-06-05
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Expires: 1992-02-11
Abstract
Abstract This distributor may be thought of as an interfacing circuit for use between a digital computer and peripheral equipment, such as a telephone exchange, controlled by the computer. The components of the peripheral equipment are bi-stable and may be operated in groups or singly. The interfacing circuit cyclically tests these bistable components through the operating program of the peripheral unit. At each test, a comparison check against the program is made.
Inventors
- 👤 J Trelut
- 👤 J Michel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:36
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54; H04Q3/545; H04Q3/54575; H04Q3/54591; G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/22
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
240 words
A circuit condition testing apparatus for testing the condition of a plurality of bistable components in each of a plurality of peripheral units of a digital computer, there being a like number of said components in each unit, the invention comprising timing sequence control means, for operating said apparatus, a memory store receptive of control information From said computer for effecting the testing of said components in a selected one of said units under the control of said timing means, means responsive to the initiation of a first sequence by said timing means for recording a test control message in said memory store and means operative during said one sequence for checking the parity of the message recorded in said store, means responsive to a finding of parity for triggering said timing means into a later sequence, means operative during a first period of said later sequence to activate the selected one of said units whose address has been stored as part of said test control message, means for setting the plurality of components in said selected unit in one of a plurality of predetermined patterns responsive to said test control message, means operative during a second period of said later sequence for comparing the response of each of said components to said setting against the pattern recorded in said test control message, and means responsive to said comparison for indicating the results of said comparison testing to said computer.
Claim 2
Dependent Claim
240 words
A circuit condition testing apparatus for testing the condition of a plurality of bistable components in each of a plurality of peripheral units of a digital computer, there being a like number of said components in each unit, the invention comprising timing sequence control means, for operating said apparatus, a memory store receptive of control information From said computer for effecting the testing of said components in a selected one of said units under the control of said timing means, means responsive to the initiation of a first sequence by said timing means for recording a test control message in said memory store and means operative during said one sequence for checking the parity of the message recorded in said store, means responsive to a finding of parity for triggering said timing means into a later sequence, means operative during a first period of said later sequence to activate the selected one of said units whose address has been stored as part of said test control message, means for setting the plurality of components in said selected unit in one of a plurality of predetermined patterns responsive to said test control message, means operative during a second period of said later sequence for comparing the response of each of said components to said setting against the pattern recorded in said test control message, and means responsive to said comparison for indicating the results of said comparison testing to said computer.
Claim 3
Dependent Claim
29 words
An apparatus as claimed in claim 1 further comprising means responsive to a failure to find parity in said one sequence for stopping said timing means from further sequence.
Claim 4
Dependent Claim
54 words
An apparatus as claimed in claim 2, wherein there are transfer means responsive to said parity failure for indicating said failure to said computer for transferring the message stored in said memory store to said computer, and means responsive to a further a signal from said timing means for resetting said timing control means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-04 | 1976-12-04 | 1977-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-04 | 1980-12-04 | 1981-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-04 | 1984-12-04 | 1985-06-05 | $7700.00 | Window Closed / Lapsed |