US3737672A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low-level logic protection interface
Assignee: EAGLE SIGNAL CONTROLS CORP A CORP OF DE
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Filing: 1971-06-04
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Granted: 1973-06-05
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Expires: 1991-06-04
Abstract
Abstract A low-level logic protection interface deriving operating potential from alternating-current line voltage is provided for coupling low-voltage, direct-current, detector signals of the order of zero to 12 volts, for example, to solid state control circuits. The interface serves to provide at least 12 volts noise immunity in such control circuits and to protect the control circuits against damage by the accidental connection of the alternating-current line as well as to protect against momentary high voltage transients. An inverter integrated circuit and an output transistor are provided with a back-biased diode and a zener diode interposed in the input to the inverter integrated circuit. Consequently, with a high positive input from the alternating-current line circuit, the output transistor cannot be turned on. With high positive input the diode is back-biased and with negative input the voltage applied to the zener diode is too low to cause the zener diode to conduct.
Inventors
- 👤 F Hill
- 👤 G Fieser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:07
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00307
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
224 words
A low-level logic protection circuit for driving first and second logic outputs with first and second logic signal inputs, said circuit including first and second interfaces, each of said interfaces comprising: first and second parallel branches, said first branch extending between a common point and an input signal terminal, said second branch extending between said common point and a fixed potential terminal, means coupling a selected point of said second branch To a device for creating one of said logic outputs, a first diode in said first branch poled to allow current flow in said first branch and from said common point, a second diode in said second branch for allowing current flow in said second branch and from said common point, limiting means in said second branch between said common point and said selected point for allowing current flow in said second branch only when voltage across said limiting means exceeds a predetermined value, and a resistor between said selected point and said fixed potential; and, a common power supply means including first and second input terminals adapted to be connected to an alternatingcurrent power supply, a rectifier means connected to at least one of said terminals and having a direct current output lead, and circuit means for connecting said lead to each of said common points of said first and second interfaces.
Claim 2
Dependent Claim
224 words
A low-level logic protection circuit for driving first and second logic outputs with first and second logic signal inputs, said circuit including first and second interfaces, each of said interfaces comprising: first and second parallel branches, said first branch extending between a common point and an input signal terminal, said second branch extending between said common point and a fixed potential terminal, means coupling a selected point of said second branch To a device for creating one of said logic outputs, a first diode in said first branch poled to allow current flow in said first branch and from said common point, a second diode in said second branch for allowing current flow in said second branch and from said common point, limiting means in said second branch between said common point and said selected point for allowing current flow in said second branch only when voltage across said limiting means exceeds a predetermined value, and a resistor between said selected point and said fixed potential; and, a common power supply means including first and second input terminals adapted to be connected to an alternatingcurrent power supply, a rectifier means connected to at least one of said terminals and having a direct current output lead, and circuit means for connecting said lead to each of said common points of said first and second interfaces.
Claim 3
Dependent Claim
28 words
The circuit as defined in claim 1 wherein said connecting circuit means includes a resistor between said lead and said common points of said first and second interfaces.
Claim 4
Dependent Claim
24 words
A circuit as defined in claim 1 wherein said limiting means is a zener diode having a break-down voltage corresponding with said predetermined value.
Claim 5
Dependent Claim
14 words
A circuit as defined in claim 1 wherein said first input terminal is grounded.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-04 | 1976-12-04 | 1977-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-04 | 1980-12-04 | 1981-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-04 | 1984-12-04 | 1985-06-05 | $7700.00 | Window Closed / Lapsed |