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US3737638A Expired / Lapsed US ⏱️ 0.0 years remaining

A series-parallel multiplication device using modified two{40 s complement arithmetic

Assignee: International Business Machines Corp
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Filing: 1972-07-18
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Granted: 1973-06-05
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Expires: 1992-07-18
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Abstract

Abstract A serial para lel multiplication device in which the digits of the multiplicand are coded in two''s complement and in which the digits of the multiplier are coded in two''s complement modified by inverting the highest ranking digit and appending another digit of predetermined value as the last digit, the appended digit having the same rank as the lowest ranking digit. The devie produces a series of partial products, each partial product being formed by logically combining the inverse of the ith multiplier digit with each multiplicand digit. As a consequence, each partial product digit assumes one value if the correspondingly ranking multiplicand and ith multiplier digits match and another value if they mismatch. The partial product is then corrected by adding to it the value of the ith digit.

Inventors

  • 👤 D Esteban

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 14:15
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/527; G06F7/5272; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3832

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 152 words
In a serial-parallel multiplication device in which each digit of a multiplicand A (FIG. 3-RA) in two''s complement form is logically combined with a digit of a multiplier X (FIG. 3-RX) also in two''s complement form to yield a partial product; the combination comprising: means (FIGS. 1 or 2) for modifying the multiplier by inverting the highest ranking digit and appending another digit of predetermined value as the last digit, the appended digit having the same rank as the lowest ranking digit; logic means (FIG. 3-I, XOR3 to 6) for inverting each modified multiplier digit and for combinaing the ith modified multiplier digit with each multiplicand digit, each combined digit assuming one binary value if the corresponding ranked multiplicand and ith multiplier digits match and another binary value if they mismatch; and means (FC, FIG. 6) for summing the combined digits and the ith modified multiplier digit to form the partial product.
Claim 2
Dependent Claim 152 words
In a serial-parallel multiplication device in which each digit of a multiplicand A (FIG. 3-RA) in two''s complement form is logically combined with a digit of a multiplier X (FIG. 3-RX) also in two''s complement form to yield a partial product; the combination comprising: means (FIGS. 1 or 2) for modifying the multiplier by inverting the highest ranking digit and appending another digit of predetermined value as the last digit, the appended digit having the same rank as the lowest ranking digit; logic means (FIG. 3-I, XOR3 to 6) for inverting each modified multiplier digit and for combinaing the ith modified multiplier digit with each multiplicand digit, each combined digit assuming one binary value if the corresponding ranked multiplicand and ith multiplier digits match and another binary value if they mismatch; and means (FC, FIG. 6) for summing the combined digits and the ith modified multiplier digit to form the partial product.
Claim 3
Dependent Claim 24 words
In a serial-parallel multiplication device according to claim 1, said device further includes: accumulator means (FIG. 6) for successively shifting and summing partial products.

References Cited (Backward Citations)

US3489888A Cited
US3519809A Cited
US3627999A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-06-04 1976-12-04 1977-06-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-06-04 1980-12-04 1981-06-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-06-04 1984-12-04 1985-06-05 $7700.00 Window Closed / Lapsed

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