US3737588A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed semiconductor switching circuit
Assignee: GTE Sylvania Inc
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Filing: 1971-10-12
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Granted: 1973-06-05
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Expires: 1991-10-12
Abstract
Abstract Crosspoint switching array, each crosspoint switching circuit including silicon controlled switches for connecting signal lines of one group of transmission lines to signal lines of another group. Each switching circuit includes a transistor triggering arrangement connected between control lines of the two groups. Coincident pulses on the control lines cause current to flow in the triggering arrangement thereby switching the silicon controlled switches ON and providing signal paths between the two groups of lines. A leakage resistance is connected between the cathode of each silicon controlled switch and a source of biasing potential so that when the silicon controlled switches are turned OFF, stored charges are rapidly dissipated through the relatively low impedance paths provided by the leakage resistances.
Inventors
- 👤 A Susi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:52
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/52; H04Q3/521; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/72; H03K17/735; H03K2217/00; H03K2217/0036
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
346 words
A crosspoint switching array for establishing particular signal transmission paths between selected transmission line groups of first and second sets of transmission line groups, each transmission line group of the first set being associated with each transmission line group of the second set at separaTe ones of a multiplicity of crosspoints, each transmission line group having at least one signal line and a control line; said switching array comprising a controlled latching semiconductor device for each signal transmission path between a transmission line group of the first set and a transmission line group of the second set at each crosspoint, each of said semiconductor devices having first and second signal electrodes and a gate electrode, and having a conducting condition and a non-conducting condition, the first and second signal electrodes being adapted to be connected between signal lines in said first and second sets of transmission line groups; a resistance for each controlled latching semiconductor device connected between the gate electrode and the second signal electrode of the associated semiconductor device; triggering means at each crosspoint adapted to be connected between the control lines in said first and second sets of transmission line groups for coupling switching pulses occurring across the control lines to the gate electrodes of the controlled latching semiconductor devices at the crosspoint; the application of coincident pulses to selected control lines of said first and second sets of transmission line groups causing current flow from the triggering means at the selected crosspoints to the gate electrodes of associated controlled latching semiconductor devices to thereby switch the controlled latching semiconductor devices from the non-conducting condition to the conducting condition and establish particular signal transmission paths between the selected transmission line groups; and a leakage impedance for each controlled latching semiconductor device having one terminal connected to the second signal electrode and a second terminal adapted to be connected to a source of reference potential for providing a leakage path for stored charges in the controlled latching semiconductor device when the controlled latching semiconductor device changes from the conducting condition to the non-conducting condition.
Claim 2
Dependent Claim
346 words
A crosspoint switching array for establishing particular signal transmission paths between selected transmission line groups of first and second sets of transmission line groups, each transmission line group of the first set being associated with each transmission line group of the second set at separaTe ones of a multiplicity of crosspoints, each transmission line group having at least one signal line and a control line; said switching array comprising a controlled latching semiconductor device for each signal transmission path between a transmission line group of the first set and a transmission line group of the second set at each crosspoint, each of said semiconductor devices having first and second signal electrodes and a gate electrode, and having a conducting condition and a non-conducting condition, the first and second signal electrodes being adapted to be connected between signal lines in said first and second sets of transmission line groups; a resistance for each controlled latching semiconductor device connected between the gate electrode and the second signal electrode of the associated semiconductor device; triggering means at each crosspoint adapted to be connected between the control lines in said first and second sets of transmission line groups for coupling switching pulses occurring across the control lines to the gate electrodes of the controlled latching semiconductor devices at the crosspoint; the application of coincident pulses to selected control lines of said first and second sets of transmission line groups causing current flow from the triggering means at the selected crosspoints to the gate electrodes of associated controlled latching semiconductor devices to thereby switch the controlled latching semiconductor devices from the non-conducting condition to the conducting condition and establish particular signal transmission paths between the selected transmission line groups; and a leakage impedance for each controlled latching semiconductor device having one terminal connected to the second signal electrode and a second terminal adapted to be connected to a source of reference potential for providing a leakage path for stored charges in the controlled latching semiconductor device when the controlled latching semiconductor device changes from the conducting condition to the non-conducting condition.
Claim 3
Dependent Claim
70 words
A crosspoint switching array in accordance with claim 1 wherein each of said controlled latching semiconductor devices is operable to be biased in the non-conducting condition so as to cause switching to the conducting condition in response to a momentary flow of current to the gate electrode whereby current from the associated triggering means switches the control latching semiconductor device to the conducting condition providing a signal transmission path therethrough.
Claim 4
Dependent Claim
87 words
A crosspoint switching array in accordance with claim 2 wherein each triggering means at each crosspoint includes a transistor means having an emitter connection for connecting to the control line of the transmission line group of one of the sets of transmission line groups, a base connection for connecting to the control line of the transmission line group of the other of the sets of transmission line groups, and a collector connection to the gate electrode of each of the controlled latching semiconductor devices at the crosspoint.
Claim 5
Dependent Claim
89 words
A crosspoint switching array in accordance with claim 3 including a blocking means connected between the gate electrode of each controlled latching semiconductor device and a collector connection of said transistor means for blocking the flow of current along a path from the signal line connected to the first signal electrode of the semiconductor device, into the semiconductor device, from the gate electrode to tyhe collector connection, through the transistor means, and from the base connection of the transistor means to the control line connected to the base connection.
Claim 6
Dependent Claim
99 words
A crosspoint switching array in accordance with claim 4 wherein each transistor means includes a transistor associated with each controlled latching semiconductor device and having its emitter connected to the emitter connection, its base connected to the base connection, and its collector connected through said blOcking means to the gate electrode of the associated controlled latching semiconductor device, all current flow between the control lines at the crosspoint being caused to flow across an emitter-base junction of the transistor means thereby causing collector current to flow into the gate electrodes of the controlled latching semiconductor devices at the crosspoint.
Claim 7
Dependent Claim
100 words
A crosspoint switching array in accordance with claim 4 wherein each transistor means includes a transistor device having an emitter electrode connected to the emitter connection, a base electrode connected to the base connection, and a separate collector electrode connected through a blocking means to the gate electrode of each of the controlled latching semiconductor devices at the crosspoint, all current flow between the control lines at the crosspoint being caused to flow across the emitter-base junction of the transistor device thereby causing collector current to flow into the gate electrodes of the controlled latching semiconductor devices at the crosspoint.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-04 | 1976-12-04 | 1977-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-04 | 1980-12-04 | 1981-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-04 | 1984-12-04 | 1985-06-05 | $7700.00 | Window Closed / Lapsed |