US3737578A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase synchronizing circuit
Assignee: NEC Corp
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Filing: 1969-06-12
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Granted: 1973-06-05
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Expires: 1989-06-12
Abstract
Abstract A phase synchronizing circuit comprises a voltage-controlled oscillator and a frequency multiplier for multiplying the output frequency of the oscillator by a factor corresponding to the number of phases in the input signal. A phase-difference detector receives both the input signal and the multipled frequency output and produces a d.c. signal representing the number of phases in the input signal.
Inventors
- 👤 Y Matsuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:56
CPC Classifications
H; H04; H04J; H04J1/00; H04J1/20
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
169 words
A phase synchronizing circuit comprising an input for receiving a polyphase phase-modulated input signal, a voltage controlled oscillator oscillating at the frequency region around the carrier frequency of the input signal, a frequency multiplier coupled to the output of said oscillator for multiplying the output frequency of said oscillator by a positive integer to produce a frequency multiplied signal, means having a first input terminal connected to the output of said frequency multiplier and receiving said frequency multiPlied signal thereat, a second input terminal coupled to said input for receiving said input signal thereat, and an output terminal for detecting the phase difference of said frequency multiplied signal and said input signal to derive at said output terminal a D.C. signal representative of the phase difference between said input signal and said frequency multiplied signal without multiplying the frequency of said input signal, and means coupled to said output terminal of said signal processing means and responsive to said D.C. signal for controlling the output signal of said oscillator.
Claim 2
Dependent Claim
169 words
A phase synchronizing circuit comprising an input for receiving a polyphase phase-modulated input signal, a voltage controlled oscillator oscillating at the frequency region around the carrier frequency of the input signal, a frequency multiplier coupled to the output of said oscillator for multiplying the output frequency of said oscillator by a positive integer to produce a frequency multiplied signal, means having a first input terminal connected to the output of said frequency multiplier and receiving said frequency multiPlied signal thereat, a second input terminal coupled to said input for receiving said input signal thereat, and an output terminal for detecting the phase difference of said frequency multiplied signal and said input signal to derive at said output terminal a D.C. signal representative of the phase difference between said input signal and said frequency multiplied signal without multiplying the frequency of said input signal, and means coupled to said output terminal of said signal processing means and responsive to said D.C. signal for controlling the output signal of said oscillator.
Claim 3
Dependent Claim
67 words
The phase synchronizing circuit of claim 1, in which said frequency multiplier comprises means for multiplying the output frequency of said oscillator by a factor of two, said phase difference detecting means comprising a diplexer for adding said input signal and the output signal of said frequency multiplier, and a non-linear element circuit having an approximate cubed characteristic and operatively connected to the output of said diplexer.
Claim 4
Dependent Claim
84 words
The phase synchronizing circuit of claim 1, in which said phase difference detecting means comprises a diplexer for adding the input signal and the frequency multiplier output, first and second semiconductor diodes connected to the output of said diplexer in parallel with reverse polarity to one another, and a low pass filter responsive to the signal appearing at the junction of the output of said diplexer, said first and second diodes, and the input of said low pass filter for deriving said D.C. signal.
Claim 5
Dependent Claim
141 words
The phase synchronizing circuit of claim 1, further comprising first means coupled to said oscillator for producing two phase shifted output signals that are in phase quadrature relation to each other, first and second phase detectors responsive to said input signal and said phase shifted output signals for detecting the in-phase component and the quadrature component of said input signal to thereby produce phase detector output signals, respectively, and second means responsive to the outputs of said first and said second detectors for producing an output signal of either polarity depending on the respective polarities of said first and said second phase detector output signals, said output frequency controlling means comprising means for multiplying the output of said second output signal producing means by said D.C. signal, and means for applying the output of said multiplier to said voltage controlled oscillator.
Claim 6
Dependent Claim
67 words
The phase synchronizing circuit of claim 1, in which said frequency multiplier comprises means for multiplying the oscillating frequency from said vol-age controlled oscillator by a number corresponding to the number of the phase states that are taken by said input signal, said phase difference detecting means including at least two diplexers and at least two non-linear element circuits, each of which has an approximate cubed characteristic.
Claim 7
Dependent Claim
59 words
The phase synchronizing circuit of claim 1, in which said frequency multiplier comprises means for multiplying the oscillating frequency from said voltage controlled oscillator by a number corresponding to the number of the phase states that are taken by said input signal, said phase difference detecting means including means for multiplying said input signal and said frequency multiplied signal.
Claim 8
Dependent Claim
21 words
The phase synchronizing circuit of claim 6, in which said signal processing means further comprises at least one non-linear circuit element.
References Cited (Backward Citations)
US2369663A
Cited
US3065427A
Cited
US3196369A
Cited
US3353101A
Cited
US3100871A
Cited
US3518680A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-04 | 1976-12-04 | 1977-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-04 | 1980-12-04 | 1981-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-04 | 1984-12-04 | 1985-06-05 | $7700.00 | Window Closed / Lapsed |