US3735394A
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Integrating a-d conversion system
Assignee: Individual
•
Filing: 1970-10-27
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Granted: 1973-05-22
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Expires: 1990-10-27
Abstract
Abstract An integrating A-D conversion system which is adapted to provide an analog input voltage in the form of a binary-coded decimal digital output indicated by a code 8-4-2-1 and comprises the steps of (1) positively integrating a positive analog input voltage for a period of time 2T, (2) subtracting from the resulting voltage -Vr in (1) a voltage produced by integrating a negative reference voltage for a period of time T, (3) adding the resulting voltage in (2) with a negative (or positive) voltage produced by integrating the voltage -Vr(or + Vr) for a period of time T/2 according as the resulting voltage in (2) is positive (or negative), (4) adding the resulting voltage in (3) with a negative (or positive) voltage produced by integrating the voltage -Vr(or + Vr) for a period of time T/4 according as the resulting voltage in (3) is positive (or negative), (5) adding the resulting voltage in (4) with a negative (or positive) voltage produced by integrating the voltage -Vr(or + Vr) for a period of time T/8 according as the resulting voltage in (4) is positive (or negative), (6) adding the resulting voltage in (5) with a negative (or positive) voltage produced by integrating the voltage -Vr(or + Vr) for a period of time T/8 according as the resulting voltage in (5) is positive (or negative), (7) obtaining a digital output representing the first digit of a binary-coded decimal number in the form of a four-bit code of ''''1'''' and ''''0'''' according as each of the resulting voltages in (2), (3), (4) and (5) is positive or negative, and (8) thereafter repeating the same operations as in (2) to (7) to obtain digital outputs representing a second, third, . . . digits in the form of binarycoded decimal numbers.
Inventors
- 👤 T Eto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:19
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
373 words
An integrating A-D conversion method for converting an analog input voltage into a digital output in the form of a binary-coded decimal number each digit of which is represented by a code consisting of first, second, third and fourth bits having weights 8, 4, 2 and 1 respectively, which comprises the sequential steps of, A10: integrating a positive (or negative) analog input voltage by first integrating means for a predetermined period of time 2T, to obtain an output, A11: reducing the output by integrating a first negative (or positive) reference voltage by the first integrating means for a period of time T and storing a digital signal ''''1'''' (or ''''0'''') in a first storage means when the output derived from the first integrating means at the end of the step A11 is positive (or negative), A12: further reducing the remaining output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/2 and storing a digital signal ''''1'''' (or ''''0'''') in a second storage means when an output derived from the first integrating means at the end of the step A12 is positive (or negative), A13: further reducing the remaining output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/4 and storing a digital signal ''''1'''' (or ''''0'''') in a third storing means when an output derived from the first integrating means at the end of the step A13 is positive (or negative), A14: further reducing the remaining output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/8 and storing a digital signal ''''1'''' (or ''''0'''') in a fourth storage means when an output derived from the first integrating means at the end of the step A14 is positive (or negative), B1: applying digital signals stored in the first, second, third and fourth storage means to the most significant digit portion of a storage and output circuit to store them therein, thereby providing a digital output of a binary-coded decimal number having the most significant digit represented by the digital signals stored in the most significant digit portion of the storage circuit.
Claim 2
Dependent Claim
373 words
An integrating A-D conversion method for converting an analog input voltage into a digital output in the form of a binary-coded decimal number each digit of which is represented by a code consisting of first, second, third and fourth bits having weights 8, 4, 2 and 1 respectively, which comprises the sequential steps of, A10: integrating a positive (or negative) analog input voltage by first integrating means for a predetermined period of time 2T, to obtain an output, A11: reducing the output by integrating a first negative (or positive) reference voltage by the first integrating means for a period of time T and storing a digital signal ''''1'''' (or ''''0'''') in a first storage means when the output derived from the first integrating means at the end of the step A11 is positive (or negative), A12: further reducing the remaining output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/2 and storing a digital signal ''''1'''' (or ''''0'''') in a second storage means when an output derived from the first integrating means at the end of the step A12 is positive (or negative), A13: further reducing the remaining output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/4 and storing a digital signal ''''1'''' (or ''''0'''') in a third storing means when an output derived from the first integrating means at the end of the step A13 is positive (or negative), A14: further reducing the remaining output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/8 and storing a digital signal ''''1'''' (or ''''0'''') in a fourth storage means when an output derived from the first integrating means at the end of the step A14 is positive (or negative), B1: applying digital signals stored in the first, second, third and fourth storage means to the most significant digit portion of a storage and output circuit to store them therein, thereby providing a digital output of a binary-coded decimal number having the most significant digit represented by the digital signals stored in the most significant digit portion of the storage circuit.
Claim 3
Dependent Claim
380 words
An integrating A-D conversion method according to claim 1, which further comprises the sequential steps at least A21, A22, A23, A24 and B2 following the steps A10, A11, A12, A13, A14 and B1, in which: A21: further reducing the output by integrating the first negative (or positive) reference voltage by second integrating means for a period of time T and storing a digital signal ''''1'''' (or ''''0'''') in the first storage means when an output derived from the second integrating means at the end of the step A21 is positive (or negative), the second integrating means being the same as the first integrating means except that the integrating constant thereof is ten times that of the first integrating means, A22: further reducing the output by integrating the first negative (or positive) reference voltage by the second integrating means for a period of time T/2 and storing a digital signal ''''1'''' (or ''''0'''') in the second storage means when an output derived from the second integrating means at the end of the step A22 is positive (or negative), A23: further reducing the output by integrating the first negative (or positive) reference voltage by the second integrating means for a period of time T/4 and storing a digital signal ''''1'''' (or ''''0'''') in the third storage means when an output derived from the second integrating means at the end of the step A23 is positive (or negative), A24: further reducing the output by integrating the first negative (or positive) reference voltage by the second integrating means for a period of time T/8 and storing a digital signal ''''1'''' (or ''''0'''') in the fourth storage means when an output derived from the second integrating means at the end of the step A24 is positive (or negative), B2: applying the digital signals stored in the first, second, third and fourth storage means to the less significant digit portion immediately following the most significant one of the storage circuit to store them therein, thereby providing a digital output of a binary-coded decimal number having the most significant digit and the next less significant digit immediately following the most significant one and represented by the digital signals stored in the most significant digit portion and the immediately next less significant digit portion of the storage circuit.
Claim 4
Dependent Claim
353 words
An integrating A-D conversion method according to claim 1, which further comprises the sequential steps at least A21, A22, A23, A24 and B2 following the steps A10, A11, A12, A13, A14 and B1, in which, A21: further reducing the output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/10 and storing a digital signal ''''1'''' (or ''''0'''') in the first storage means when an output derived from the first integrating means at the end of the step A21 is positive (or negative), A22: further reducing the output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/20 and storing a digital signal ''''1'''' (or ''''0'''') in the second storage means when an output derived from the first integrating means at the end of the step A22 is positive (or negative), A23: furTher reducing the output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/40 and storing a digital signal ''''1'''' (or ''''0'''') in the third storage means when an output derived from the first integrating means at the end of the step A23 is positive (or negative), A24: further reducing the output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/80 and storing a digital signal ''''1'''' (or ''''0'''') in the fourth storage means when an output derived from the first integrating means at the end of the step A24 is positive (or negative), B2: applying the digital signals stored in the first, second, third and fourth storage means to the next less significant digit portion immediately following the most significant one of the storage circuit to store them therein, thereby providing a digital output of a binary-coded decimal number having the most significant digit and the less significant digit immediately following the most significant one and represented by the digital signals stored in the most significant digit portion and the immediately less significant digit portion of the storage circuit.
Claim 5
Dependent Claim
388 words
An integrating A-D conversion method according to claim 1, which further comprises the sequential steps at least A21, A22, A23, A24 and B2 following the steps A10, A11, A12, A13, A14 and B1, in which A21: further reducing the output by integrating a second negative (or positive) reference voltage by the first integrating means for a period of time T and storing a digital signal ''''1'''' (or ''''0'''') in the first storage means when an output derived from the first integrating means at the end of the step A21 is positive (or negative), the second negative (or positive) reference voltage being the same as the first negative (or positive) reference voltage except that the value thereof is one-tenth of that of the first negative (or positive) reference voltage, A22: further reducing the output by integrating the second negative (or positive) reference voltage by the first integrating means for a period of time T/2 and storing a digital signal ''''1'''' (or ''''0'''') in the second storage means when an output derived from the first integrating means at the end of the step A22 is positive (or negative), A23: further reducing the output by integrating the second negative (or positive) reference voltage by the first integrating means for a period of time T/4 and storing a digital signal ''''1'''' (or ''''0'''') in the third storage means when an output derived from the first integrating means at the end of the step A23 is positive (or negative), A24 : further reducing the output by integrating the second negative (or positive) reference voltage by the first integrating means for a period of time T/80 and storing a digital signal ''''1'''' (or ''''0'''') in the fourth storage means when an output derived from the first integrating means at the end of the step A24 is positive (or negative), B2: applying the digital signals stored in the first, second, third and fourth storage means to the less significant digit portion immediately following the most significant one of the storage circuit to store them therein, thereby providing a digital output of a binary-coded decimal number having the most significant digit and the less significant digit immediately following the most significant one and represented by the digital signals stored in the most significant digit portion and the immediately less significant digit portion of the storage circuit.
Claim 6
Dependent Claim
386 words
An integrating A-D conversion method aCcording to claim 1, which further comprises the sequential steps of C, A21, A22, A23, A24, and B2 following the steps A10, A11, A12, A13, A14 and B1, in which C: increasing the output voltage of the first integrating means to a voltage the value of which is ten times that of the output voltage obtained at the end of the step A14 , A21: reducing the increased voltage by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T and storing a digital signal ''''1'''' (or ''''0'''') in the first storage means when an output derived from the first integrating means at the end of the step A21 is positive (or negative), A22: further reducing the output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/2 and storing a digital signal ''''1'''' (or ''''0'''') in the second storage means when an output derived from the first integrating means at the end of the step A22 is positive (or negative), A23: further reducing the output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/4 and storing a digital signal ''''1'''' (or ''''0'''') in the third storage means when an output derived from the first integrating means at the end of the step A23 is positive (or negative), A24: further reducing the output by integrating the first negative (or positive) reference voltage by the first integrating means for a period of time T/8 and storing a digital signal ''''1'''' (or ''''0'''') in the fourth storage means when an output derived from the first integrating means at the end of the step A24 is positive (or negative), B2: applying the digital signals stored in the first, second, third and fourth storage means to the less significant digit portion immediately following the most significant one of the storage circuit to store them therein, thereby providing a digital output of a binary-coded decimal number having the most significant digit and the less significant digit immediately following the most significant one and represented by the digital signals stored in the most significant digit portion and the immediately less significant digit portion of the storage circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-21 | 1976-11-20 | 1977-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-21 | 1980-11-20 | 1981-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-21 | 1984-11-20 | 1985-05-22 | $7700.00 | Window Closed / Lapsed |