Bipolar analog-to-digital converter with double detection of the sign bit

Claim 2

An analog-to-digital converter for converting an analog signal into a digital code comprising: a source of samples of an analog signal; means for sequentially generating the bits of the digital code for a particular sample of the analog signal, the first digit generated being indicative of the sign of the sample of the analog signal; means for determining the sign of the sample of the analog signal at a preselected time after the generation of the first bit of the digital code and before the entire code for that sample has been generated, and generating a subsequent sign bit in response to the check; and means for comparing the first bit of the digital code with the subsequent sign bit and correcting the digital code when the sign bits differ.

Claim 3

A sequential analog-to-digital converter circuit which generates a digital representation of samples of bipolar input signals comprising: means for generating timing pulses; means responsive to the timing pulses for sampling the amplitude of the input signals and maintaining the sampled amplitude for a first period of time; an analog comparison means having two inputs for Comparing the amplitude of signals applied to its inputs and generating digital bits in response to the comparison, the sampled amplitude being applied to a first input of said comparison means; means for generating control signals in response to the digital bits and the timing pulses; decoding means having a plurality of stages for producing an equivalent analog signal by activating stages of said decoding means in response to the control signal, the equivalent analog signal being applied to a second input of said comparison means; means for checking the stages of said decoding means after a preselected number of digital bits have been generated for forcing the equivalent analog signal to be zero for a fixed period of time whenever the stages are in predetermined conditions; a digital comparison means having two inputs for comparing the digital bit generated by said analog comparison means during the fixed period of time with the first digital bit generated for the sampled amplitude and generating an output when the bits differ; means for continuing the analog-to-digital conversion after the fixed period of time has ended; and output means for generating the output of said converter circuit in response to the state of the stages of said decoding means and the output of said digital comparison means.

Claim 4

A sequential analog-to-digital converter circuit which generates a digital representation of samples of bipolar input signals comprising: means for generating timing pulses; means responsive to the timing pulses for sampling the amplitude of the input signals and maintaining the sampled amplitude for a first period of time; an analog comparison means having two inputs for Comparing the amplitude of signals applied to its inputs and generating digital bits in response to the comparison, the sampled amplitude being applied to a first input of said comparison means; means for generating control signals in response to the digital bits and the timing pulses; decoding means having a plurality of stages for producing an equivalent analog signal by activating stages of said decoding means in response to the control signal, the equivalent analog signal being applied to a second input of said comparison means; means for checking the stages of said decoding means after a preselected number of digital bits have been generated for forcing the equivalent analog signal to be zero for a fixed period of time whenever the stages are in predetermined conditions; a digital comparison means having two inputs for comparing the digital bit generated by said analog comparison means during the fixed period of time with the first digital bit generated for the sampled amplitude and generating an output when the bits differ; means for continuing the analog-to-digital conversion after the fixed period of time has ended; and output means for generating the output of said converter circuit in response to the state of the stages of said decoding means and the output of said digital comparison means.

Claim 5

A sequential analog-to-digital converter circuit which generates a digital representation of samples of bipolar input signals comprising: a source of timing pulses; a multiplex sample and hold circuit responsive to the timing signals for sequentially sampling the amplitude of a plurality of bipolar input signals and holding the samples while a digital representation of each is generated; an analog comparator having two inputs for comparing the amplitude of signals applied to its inputs, and generating a digital ''''1'''' when the signal applied to a first input is more positive than the signal applied to a second input, and a digital ''''0'''' when it is not, the samples of the input signal from said multiplex sample and hold circuit being applied to the first of said analog comparator; a logic circuit for generating a first set of control signals in response to the output of said analog comparator and the timing pulses; a decoder having a plurality of stages activated by the first set of control signals, said decoder producing an equivalent analog output signal that is the summation of the weighted outputs of its stages, the equivalent analog output signal being applied to the second input of said analog comparator; a partial decoder having a plurality of stages activated by a second set of control signals, said partial decoder producing an output signal that is dependent on the stage activated, the output signal of said partial decoder being summed with the equivalent analog output signal of said decoder at the second input of said analog comparator; an error control circuit for producing the second set of control signals after a preselected number of the digital bits of the code have been generated in response to the state of the stages of said decoder and the timing pulses, the second set of control signals operating on said partial decoder so as to cause the signal at the second input of said analog comparator to be zero for a fixed period of time when the bits generated have predetermined codes, the second set of control signals also operating subsequently on said partial decoder in response to the output of said analog comparator during the fixed period of time in such a way as to correct the signal applied to the second input of said analog comparator when the first digital bit generated by the comparator for a particular sample does not match the digital bit generated during the fixed period of time; and an output circuit for producing output signals in response to the states of the stages of said decoder modified by the states of the stages of said partial decoder.

Claim 6

A sequential analog-to-digital converter circuit which generates a digital representation of samples of bipolar input signals comprising: a source of timing pulses; a multiplex sample and hold circuit responsive to the timing signals for sequentially sampling the amplitude of a plurality of bipolar input signals and holding the samples while a digital representation of each is generated; an analog comparator having two inputs for comparing the amplitude of signals applied to its inputs, and generating a digital ''''1'''' when the signal applied to a first input is more positive than the signal applied to a second input, and a digital ''''0'''' when it is not, the samples of the input signal from said multiplex sample and hold circuit being applied to the first of said analog comparator; a logic circuit for generating a first set of control signals in response to the output of said analog comparator and the timing pulses; a decoder having a plurality of stages activated by the first set of control signals, said decoder producing an equivalent analog output signal that is the summation of the weighted outputs of its stages, the equivalent analog output signal being applied to the second input of said analog comparator; a partial decoder having a plurality of stages activated by a second set of control signals, said partial decoder producing an output signal that is dependent on the stage activated, the output signal of said partial decoder being summed with the equivalent analog output signal of said decoder at the second input of said analog comparator; an error control circuit for producing the second set of control signals after a preselected number of the digital bits of the code have been generated in response to the state of the stages of said decoder and the timing pulses, the second set of control signals operating on said partial decoder so as to cause the signal at the second input of said analog comparator to be zero for a fixed period of time when the bits generated have predetermined codes, the second set of control signals also operating subsequently on said partial decoder in response to the output of said analog comparator during the fixed period of time in such a way as to correct the signal applied to the second input of said analog comparator when the first digital bit generated by the comparator for a particular sample does not match the digital bit generated during the fixed period of time; and an output circuit for producing output signals in response to the states of the stages of said decoder modified by the states of the stages of said partial decoder.

Claim 7

A sequeNtial analog-to-digital converter as claimed in claim 3 wherein said decoder comprises: five flip-flops whose states are controlled by the first set of control signals; five switches each responsive to a separate one of said five flip-flops; a first negative reference voltage applied to one terminal of the first switch of said five switches; a first positive reference voltage applied to one terminal of the second, third, fourth and fifth switches of said five switches, said positive reference voltage being equal in magnitude to said negative reference voltage; and five resistors each having one end connected to the output of the decoder and each having the other end connected to the other terminal of a separate one of said five switches, the resistor connected to said first switch having a relative resistance R, and the resistances connected to said second, third, fourth and fifth switches having relative resistances of 2R, 4R, 8R and 16R, respectively.

Claim 8

A sequential analog-to-digital converter as claimed in claim 3 wherein said error control circuit comprises: a three-input AND gate for generating an output level whenever the states of said decoder indicate that the first three bits generated by said converter are (111); a three-input NOR gate for generating an output level whenever the states of said decoder indicate that the first three bits generated by said converter are (000); a two-input AND gate having the output of said three-input AND gate applied to one of its inputs and the third timing pulse after the start of the coding process applied to its other input, the output of said two-input AND gate being one of the second set of control signals; a two-input OR gate having the output of said three-input AND gate applied to one input and the output of said three-input NOR gate applied to the other input; and a three-input INHIBIT AND gate having the output of said two-input OR gate applied to one input, the fourth timing pulse after the start of the coding process applied to the other input, and the output of said analog comparator applied to its INHIBIT input, the output of said two-input INHIBIT AND gate being another of second set of control signals.

Claim 9

A sequential analog-to-digital converter as claimed in claim 3 wherein said correction circuit comprises: three two-input INHIBIT AND gates each having its input responsive to the state of a separate one of the first three stages of said decoder, the INHIBIT inputs of all of said three two-input INHIBIT AND gates being responsive to the state of the first stage of said partial decoder; and three two-input OR gates each having one input connected to a separate one of the outputs of said three two-input INHIBIT AND gates, the other inputs of all of said three two-input OR gates being responsive to the state of the second stage of said partial decoder, the outputs of said three two-input OR gates being the first three bits of the output code of said converter.

Claim 10

A sequential analog-to-digital converter as claimed in claim 3 wherein said partial decoder comprises: first and second partial decoder flip-flops whose states are controlled by the second set of control signals; first and second partial decoder switches, said first partial decoder switch being responsive to said first partial decoder flip-flop and said second partial decoder switch being responsive to said second partial decoder flip-flop; a partial decoder positive reference voltage applied to one terminal of said first partial decoder switch; a partial decoder negative reference voltage applied to one terminal of said second partial decoder switch; a first partial decoder resistor connected between the output of said partial decoder and the other end of said first partial decoder switch; and a second partial decoder resistor connected between the output of said paRtial decoder and the other end of said second partial decoder switch.

Claim 11

A sequential analog-to-digital converter circuit which generates a digital representation of samples of bipolar input signals comprising: a source of timing pulses; a multiplex sample and hold circuit responsive to the timing pulses for sequentially sampling the amplitude of a plurality of bipolar input signals and holding those samples while the digital representation of each is generated; a first analog comparator having two inputs for connecting the amplitude of two signals applied to its inputs, and generating a digital output depending on which input is more positive and an analog output depending on the difference in the amplitude of two signals, the samples of the input signal from said sample and hold circuit being applied to a first input of said first analog comparator; a first logic circuit which generates a first set of control signals in response to the digital output of said first analog comparator and the timing pulses; a first decoder having a plurality of states activated by the first set of control signals, said first decoder producing a first equivalent analog output signal that is the summation of the weighted outputs of its stages, the first equivalent analog output signal being applied to the second input of said first analog comparator; a second analog comparator having two inputs for comparing the amplitude of the two signals applied to it and generating a digital output depending on which input is more positive, the analog output of said first analog comparator being applied to a first input of said second analog comparator; a second decoder having a plurality of stages activated by a second set of control signals, said second decoder producing a second equivalent analog output signal that is the summation of the weighted outputs of its stages, the second equivalent analog output signal being applied to a second input of said second analog comparator; a second logic circuit which generates the second set of control signals after said first set of control signals has been generated, said second set of control signals being generated in response to the digital output of said second analog comparator, the timing pulses, and the state of the stages of said first decoder, the second set of control signals operating on said second decoder so as to cause the signal at the second input of said second analog comparator to be zero for a fixed period of time when the states of the stages of said first decoder indicate a code near zero, the second set of control signals also operating subsequently on said second decoder in response to the output of said second analog comparator during the fixed period of time in such a way as to correct the signal applied to the second input of said second analog comparator when the first digital bit generated by said first analog comparator for a particular sample does not match the digital bit generated by said second analog comparator during the fixed period of time; and an output circuit for producing the output signals of the converter circuit in response to the states of said first and second decoder, and said second logic circuit.

Claim 12

A sequential analog-to-digital converter circuit which generates a digital representation of samples of bipolar input signals comprising: a source of timing pulses; a multiplex sample and hold circuit responsive to the timing pulses for sequentially sampling the amplitude of a plurality of bipolar input signals and holding those samples while the digital representation of each is generated; a first analog comparator having two inputs for connecting the amplitude of two signals applied to its inputs, and generating a digital output depending on which input is more positive and an analog output depending on the difference in the amplitude of two signals, the samples of the input signal from said sample and hold circuit being applied to a first input of said first analog comparator; a first logic circuit which generates a first set of control signals in response to the digital output of said first analog comparator and the timing pulses; a first decoder having a plurality of states activated by the first set of control signals, said first decoder producing a first equivalent analog output signal that is the summation of the weighted outputs of its stages, the first equivalent analog output signal being applied to the second input of said first analog comparator; a second analog comparator having two inputs for comparing the amplitude of the two signals applied to it and generating a digital output depending on which input is more positive, the analog output of said first analog comparator being applied to a first input of said second analog comparator; a second decoder having a plurality of stages activated by a second set of control signals, said second decoder producing a second equivalent analog output signal that is the summation of the weighted outputs of its stages, the second equivalent analog output signal being applied to a second input of said second analog comparator; a second logic circuit which generates the second set of control signals after said first set of control signals has been generated, said second set of control signals being generated in response to the digital output of said second analog comparator, the timing pulses, and the state of the stages of said first decoder, the second set of control signals operating on said second decoder so as to cause the signal at the second input of said second analog comparator to be zero for a fixed period of time when the states of the stages of said first decoder indicate a code near zero, the second set of control signals also operating subsequently on said second decoder in response to the output of said second analog comparator during the fixed period of time in such a way as to correct the signal applied to the second input of said second analog comparator when the first digital bit generated by said first analog comparator for a particular sample does not match the digital bit generated by said second analog comparator during the fixed period of time; and an output circuit for producing the output signals of the converter circuit in response to the states of said first and second decoder, and said second logic circuit.