Digital processor having variable length addressing

Claim 2

In a character oriented data processing system having variable length stored instructions in which binary-coded decimal digits may be arranged according to different predetermined formats, particular instruction formats having at least one address field, the address field being of at least two different possible numbers of digits in length, apparatus comprising an addressable memory for storing said instructions, means for reading out the digits of an instruction sequentially, address storing means, means responsive to a preselected digit in an address field of the instruction after the digit is read out of memory and the digit has a predetermined value for transferring a first predetermined number of address digits from memory to the address storing means, and means responsive to said preselected digit when it is not said predetermined value for transferring a second predetermined number of address digits from memory to the address storing means.

Claim 3

Apparatus as defined in claim 1 wherein the second predetermined number of address digits transferred to memory is smaller than said first predetermined number of digits.

Claim 4

Apparatus as defined in claim 1 wherein said means for transferring the second predetermined number of address digits includes means for transferring said preselected digit as one of the address digits to the address storing means.

Claim 5

Apparatus as defined in claim 3 wherein said last named means stores said preselected digit as the most significant digit of the group of address digits stored in the address storage means.

Claim 6

In a data processing system in which instructions are stored in an addressable memory, the instructions having a first group of digits coded to indicate the required operation to be executed by the precessing system and having at least one additional group of digits specifying a relative address of data locations in memory, apparatus for fetching an instruction from memory comprising control means for reading the digits of a particular instruction out of the memory in sequence starting with its said first group of digits, said control means including means responsive to the first group of digits for reading out the digits of one or more additional groups of digits of the instruction in sequence, address storage addresses, for storing a plurality of address, means responsive to a predetermined one of the digits of each of said additional groups of digits after it is read out of memory for controlling the number of digits in each of said additional group of digits read out of memory, and means transferring said additional groups of digits to said address storage means.

Claim 7

In a data processing system in which instructions are stored in an addressable memory, the instructions having a first group of digits coded to indicate the required operation to be executed by the precessing system and having at least one additional group of digits specifying a relative address of data locations in memory, apparatus for fetching an instruction from memory comprising control means for reading the digits of a particular instruction out of the memory in sequence starting with its said first group of digits, said control means including means responsive to the first group of digits for reading out the digits of one or more additional groups of digits of the instruction in sequence, address storage addresses, for storing a plurality of address, means responsive to a predetermined one of the digits of each of said additional groups of digits after it is read out of memory for controlling the number of digits in each of said additional group of digits read out of memory, and means transferring said additional groups of digits to said address storage means.

Claim 8

The apparatus of claim 5 wherein said means responsive to a predetermined one of the digits includes means sensing when said predetermined digit has a unique coded value, means responsive to said sensing means for storing said digit in the address storage means as part of said group of digits stored as an address only when the sensing means determines the digit is not said unique coded value.

Claim 9

An addressable memory for Storing binary-coded decimal digits representing variable length instructions and data, fetch control means for reading out the digits of an instruction stored in memory in sequence starting at a particular address in memory, a first register, the fetch control means including means diverting a first group of digits of the instruction into the first register, a second register, means responsive to particular digits stored in the first register for causing the fetch control means to read out at least one group of address digits into the second register, means for sensing if a predetermined one of said address digits transferred from memory to the second register is a predetermined coded value, means controlled by said sensing means when the predetermined digit has said coded value for reading out of memory and storing a first number of said address digits in the second register, and means controlled by said sensing means when the predetermined digit is not said coded value for reading out and storing a second number of said address digits in the second register.

Claim 10

An addressable memory for Storing binary-coded decimal digits representing variable length instructions and data, fetch control means for reading out the digits of an instruction stored in memory in sequence starting at a particular address in memory, a first register, the fetch control means including means diverting a first group of digits of the instruction into the first register, a second register, means responsive to particular digits stored in the first register for causing the fetch control means to read out at least one group of address digits into the second register, means for sensing if a predetermined one of said address digits transferred from memory to the second register is a predetermined coded value, means controlled by said sensing means when the predetermined digit has said coded value for reading out of memory and storing a first number of said address digits in the second register, and means controlled by said sensing means when the predetermined digit is not said coded value for reading out and storing a second number of said address digits in the second register.

Claim 11

Apparatus as defined in claim 7 wherein said predetermined coded value of the highest order digit of a group of address digits is a binary-coded decimal number greater than the decimal digit nine.

Claim 12

Apparatus as defined in claim 7 wherein said means for storing the second number of address digits stores said highest order digit with the group of address digits in the second register, and said means for storing the first number of address digits excludes said highest order digit from the group of address digits in the second register.

Claim 13

Apparatus as defined in claim 7 further including address storage means, and means for transferring the address digits from the second register to the address storage means.