Determination of yield elongation during tensile testing

Claim 2

An automated process for determining the yield elongation of a metallic substance, comprising: a. subjecting a testpiece of the substance to a tensile test; b. continuously measuring the elongation, load, and width of the testpiece; c. continuously calculating the true stress, sigma , and the true strain, Epsilon ; d. continuously calculating log sigma and log Epsilon ; e. continuously calculating simultaneous increments Delta log sigma and Delta log Epsilon in the true stress and true strain respectively, the ratio between these increments being the angular coefficient Delta log sigma / Delta log Epsilon of the log true stress/log true strain curve; f. continuously checking whether the relationship connecting Delta log sigma , Delta log Epsilon , and a given value P, is Delta log sigma / Delta log Epsilon <P or Delta log sigma / Delta log Epsilon >P; and g. recording the value of the elongation when a change occurs from the first to the second relationship.

Claim 3

An automated process as claimed in claim 1, in which when the metallic substance is a mild steel, the given value P is between 0.15 and 0.3, and the increment Delta log epsilon is a fixed number between 0.03 and 0.06.

Claim 4

An automated process as claimed in claim 1, in which the yield elongation is equal to the elongation up to the point at which Delta log sigma / Delta log epsilon becomes greater than P.

Claim 5

An automated process as claimed in claim 1, in which the checking of said relationship is not carried out until after the 0.2 percent proof stress has been reached.

Claim 6

An automated process as claimed in claim 4, further comprising in the case in which initial checking of the said relationship indicates that Delta log sigma / Delta log epsilon is greater than P, the step of performing a further test under the same conditions, whereby if the same indication is obtained, the conclusIon is drawn that there is no yield elongation.

Claim 7

A process for determining the yield elongation of a metallic substance, comprising: a. transmitting a signal representing the elongation, A, to a summator which also receives a signal representing numerical unity from a first potentiometer, the summator providing a signal representing the term (1 + A); b. transmitting the summator output signal to a first function generator providing the expression epsilon ln(1 + A), and transmitting a signal representing epsilon from the first function generator to a second function generator providing a term log epsilon ; c. transmitting the second function generator output signal representing log epsilon to a blocked first memory, and to an unblocked second memory, which records the successive values of log epsilon ; d. reversing the sign of the log epsilon signals from the second memory by means of a reversing module; e. calculating the difference between the values of log epsilon recorded by the unblocked second memory and the value stored by the first memory by transmitting the reversing module output and first memory output to a summator providing a signal representing the difference; f. comparing the said difference with a given value provided by a second potentiometer, by means of a first comparator; g. when this difference becomes equal to the given value, using the output signal of the first comparator on the one hand to cause reversal of the state of the first and second memories so that the first memory which had retained solely the last value of the term log epsilon memorized prior to blocking is unblocked and thereafter records the successive values of log epsilon whereas the second memory which had recorded the successive values of log epsilon prior to blocking is blocked and stores solely the last value of the term log epsilon prior to blocking, and on the other hand to change the sign of the given value supplied to the first comparator; h. transmitting a signal representing the load F to a divider which also receives a signal representing the width of the testpiece prior to extension from a third potentiometer; i. transmitting the output signal of the divider to a second divider which also receives a signal representing the other dimension of the testpiece prior to extension from a fourth potentiometer, this second divider then providing a signal representing the expression F/So, where So is the initial cross-section of the testpiece; j. transmitting the signal representing F/So to a multiplier module which also receives the signal representing the term (1 + A) originating from the summator, whereby a signal representing the expression F(1 + A)/So, that is to say the true stress sigma , is obtained at the output of the multiplier; k. transmitting the signal representing sigma to a function generator providing the term sigma ; l. transmitting the signal log sigma to a blocked third memory, and to an unblocked fourth memory which records the successive values of log sigma ; m. calculating the difference between the successive values of log sigma originating from the fourth memory and the value stored by the third memory by means of a summator; n. comparing this last-mentioned difference with a given value displayed by a fifth potentiometer, by means of a second comparator module, the state of the third and fourth memories, that is to say, blocked and unblocked alternately, being analogous to that of the first and second memories respectively; o. when this difference is equal to or greater than the given value, transmitting an output signal from the second comparator to a fifth memory receiving a signal representing the elongation, the state of the output signal of the second comparator being such that the memory is blocked on the value of the elongation memorized immediately before blocking, which value represenTs the yield elongation.

Claim 8

A process for determining the yield elongation of a metallic substance, comprising: a. transmitting a signal representing the elongation, A, to a summator which also receives a signal representing numerical unity from a first potentiometer, the summator providing a signal representing the term (1 + A); b. transmitting the summator output signal to a first function generator providing the expression epsilon ln(1 + A), and transmitting a signal representing epsilon from the first function generator to a second function generator providing a term log epsilon ; c. transmitting the second function generator output signal representing log epsilon to a blocked first memory, and to an unblocked second memory, which records the successive values of log epsilon ; d. reversing the sign of the log epsilon signals from the second memory by means of a reversing module; e. calculating the difference between the values of log epsilon recorded by the unblocked second memory and the value stored by the first memory by transmitting the reversing module output and first memory output to a summator providing a signal representing the difference; f. comparing the said difference with a given value provided by a second potentiometer, by means of a first comparator; g. when this difference becomes equal to the given value, using the output signal of the first comparator on the one hand to cause reversal of the state of the first and second memories so that the first memory which had retained solely the last value of the term log epsilon memorized prior to blocking is unblocked and thereafter records the successive values of log epsilon whereas the second memory which had recorded the successive values of log epsilon prior to blocking is blocked and stores solely the last value of the term log epsilon prior to blocking, and on the other hand to change the sign of the given value supplied to the first comparator; h. transmitting a signal representing the load F to a divider which also receives a signal representing the width of the testpiece prior to extension from a third potentiometer; i. transmitting the output signal of the divider to a second divider which also receives a signal representing the other dimension of the testpiece prior to extension from a fourth potentiometer, this second divider then providing a signal representing the expression F/So, where So is the initial cross-section of the testpiece; j. transmitting the signal representing F/So to a multiplier module which also receives the signal representing the term (1 + A) originating from the summator, whereby a signal representing the expression F(1 + A)/So, that is to say the true stress sigma , is obtained at the output of the multiplier; k. transmitting the signal representing sigma to a function generator providing the term sigma ; l. transmitting the signal log sigma to a blocked third memory, and to an unblocked fourth memory which records the successive values of log sigma ; m. calculating the difference between the successive values of log sigma originating from the fourth memory and the value stored by the third memory by means of a summator; n. comparing this last-mentioned difference with a given value displayed by a fifth potentiometer, by means of a second comparator module, the state of the third and fourth memories, that is to say, blocked and unblocked alternately, being analogous to that of the first and second memories respectively; o. when this difference is equal to or greater than the given value, transmitting an output signal from the second comparator to a fifth memory receiving a signal representing the elongation, the state of the output signal of the second comparator being such that the memory is blocked on the value of the elongation memorized immediately before blocking, which value represenTs the yield elongation.

Claim 9

A process as claimed in claim 6, including, to cause reversal of the state of the first and second memories and reversal of the sign of the reference voltage for the first comparator; i. feeding a signal representing twice the value of the said reference voltage into the first comparator module, the last-mentioned signal being provided by a sixth potentiometer separated from the first comparator by a switch, the output point of the first comparator being connected to the first and second memories to supply respective voltages denoted by the symbols 1-0 and 0-1; ii. when the signal representing the differences Delta log epsilon fed into the first comparator becomes equal to the value of the reference voltage for the first comparator (a) transmitting from a first output of the first comparator to the first memory a voltage 1 having the effect of unblocking the first memory and (b) transmitting from a second output of the first comparator to the second memory, a voltage 0 having the effect of blocking the second memory and of actuating the switch to connect the sixth potentiometer to the first comparator, which has the result of reversing the sign of the reference voltage of the first comparator simultaneously with the reversal of the sign of the difference Delta log epsilon caused by the reversal of the state of the first and second memories, and thereafter iii. when the new difference Delta log epsilon fed into the first comparator becomes equal to the value of the reference voltage provided by the sixth potentiometer minus the value of the reference voltage provided by the second potentiometer, (a) transmitting from the first comparator to the first memory a voltage 0 having the effect of blocking the first memory, and (b) transmitting from the first comparator to the second memory a voltage 1 having the effect of unblocking the second memory and of actuating the switch to isolate the sixth potentiometer from the first comparator, which has the result of restoring the initial reference voltage to the first comparator simultaneously with the reversal of the state of the first and second memories.

Claim 10

A method as claimed in claim 6, including, for the purpose of delaying the checking of the said relationship until after the 0.2 percent proof stress has been reached, i. transmitting the first output of the first comparator to a first OR gate, which provides a voltage 1 only when one of its two inputs receives a voltage 1 and the other input receives a voltage 0 , and otherwise provides a voltage 0; ii. transmitting the second output of the first comparator to a second OR gate similar to the first OR gate; iii. transmitting the output of a third comparator to both OR gates, the third comparator providing a voltage 1 so long as the 0.2 percent proof stress is not reached, and providing a voltage 0 when the 0.2 percent proof stress is reached; iv. transmitting the output of the first OR gate to the first and third memories; and v. transmitting the output of the second OR gate to the second and fourth memories.

Claim 11

Apparatus for determining the yield elongation of a metallic substance in the form of a testpiece, comprising: a. a tensile test machine having means for measuring the elongation, load, and width of the testpiece; b. automatic means for calculating the logarithm of the true stress, log sigma , connected to the output of the elongation measuring means and the output of the load measuring means, c. automatic means for calculating the logarithm of the true strain log epsilon connected to the output of the elongation measuring means; d. automatic means for calculating simultaneous increments Delta log sigma and Delta log epsilon in the true stress and true strain respectively; e. automatic means for comparing Delta log sigma with P Delta log epsilon , where P is a given value; and f. automatic means for recording the elongation, connected to The output of the elongation measuring means and to the output of the ratio calculating and comparing means, the recording means being actuated to store the elongation when Delta log sigma become at least equal to P Delta log epsilon .

Claim 12

Apparatus for determining the yield elongation of a metallic substance in the form of a testpiece, comprising: a. a tensile test machine having means for measuring the elongation, load, and width of the testpiece; b. automatic means for calculating the logarithm of the true stress, log sigma , connected to the output of the elongation measuring means and the output of the load measuring means, c. automatic means for calculating the logarithm of the true strain log epsilon connected to the output of the elongation measuring means; d. automatic means for calculating simultaneous increments Delta log sigma and Delta log epsilon in the true stress and true strain respectively; e. automatic means for comparing Delta log sigma with P Delta log epsilon , where P is a given value; and f. automatic means for recording the elongation, connected to The output of the elongation measuring means and to the output of the ratio calculating and comparing means, the recording means being actuated to store the elongation when Delta log sigma become at least equal to P Delta log epsilon .