Positioning control system for a machine that performs work on a moving part

Claim 2

A control circuit for comparing a feedback signal with a command signal during each cycle of a reference wave and providing an output error signal for controlling the speed of a motor in response to the difference in time of occurrence between a change from a first voltage level to a second voltage level of the feedback and the command signals and the direction of rotation of the motor in response to the order of occurrence of the voltage change of the feedback and the command signals, comprising: means including a first bistable state flip flop having a first input receiving the command signal and arranged to be switched from a first of its bistable states to a second of its bistable states by the change in the command signal when a logic 1 signal is present at a second of its inputs and arranged to remain in its first state when a logic 0 is presenT at its second input, means including a second bistable state flip flop having a first input receiving the feedback signal and arranged to be switched from the first of its bistable states to a second of its bistable states by the change in the feedback signal when a logic 1 signal is present at a second of its inputs and arranged to remain in its first state when a logic 0 is present at its second input, means responsive to the feedback signal for supplying the second input of the first flip flop with a logic 0 signal when the feedback signal is at the second voltage level and the second flip flop is in its first state, means responsive to the command signal for supplying the second input of the second flip flop with a logic 0 signal when the command signal is at the second voltage level and the first flip flop is in its first state, means responsive to an output of the first flip flop for causing the motor to be energized for rotation in one direction when the first flip flop is in its second state, means responsive to an output of the second flip flop for causing the motor to be energized for rotation in a direction opposite the said one direction when the flip flop is in its second state, and means including a third flip flop responsive to an output of the first flip flop and an output of the second flip flop for switching the first and the second flip flops to their respective first states when the first and the second flip flops are simultaneously in their second states.

Claim 3

A control circuit for comparing a coarse feedback signal and a fine feedback signal respectively with a coarse command signal and a fine command signal during each cycle of a reference wave and providing an error signal for controlling the speed of a motor in response to the difference in time of occurrence between a change from a first voltage level to a second voltage level of the feedback and the command signals and the direction of rotation of the motor in response to the order of occurrence of the voltage change of the feedback and the command signals, comprising: means including a bistable state coarse command flip flop having an input responsive to the change in the coarse command signal to condition the flip flop so the flip flop is switched from its ON to its OFF state by an input signal at its toggle and an input responsive to the change in the coarse feedback signal for maintaining the flip flop in its ON state, means including a bistable state coarse feedback flip flop having an input responsive to the change in the coarse feedback signal to condition the flip flop so the flip flop is switched from its ON to its OFF state by an input signal at its toggle and an input responsive to the change in the coarse command signal for maintaining the flip flop in its ON state, timing means including a bistable state timing flip flop having an input responsive to the changes in the coarse feedback signal and the coarse command signal and an output providing the output signals to the toggles of the coarse command flip flop and the coarse feedback flip flop for switching the conditioned coarse command flip flop or the coarse feedback flip flop from their ON to OFF states a predetermined time interval subsequent to the change in the coarse command signal or the coarse feedback signal respectively when the interval between the occurrence of the changes in the coarse command and the coarse feedback signals is greater than the predetermined interval and for maintaining the coarse command flip flop and the coarse feedback flip flops in their respective ON states when the interval between the occurrence of the changes in the coarse command and the coarse feedback signals is less than the predetermined interval, a first control means responsive to an output of the coarse command flip flop for energizing the motor for rotation in a first direction at a pre-determined speed when the coarse command flip flop is in its OFF state, a second control means responsive to an ouTput of the coarse feedback flip flop for energizing the motor for rotation in a direction opposite the first direction at a predetermined speed when the coarse feedback flip flop is in its OFF state, and a fine feedback and fine command signal comparison means operable when the coarse command and the coarse feedback flip flops are in their ON states and responsive to the fine command and fine feedback signals for respectively supplying the first and the second control means with input signals which will cause the motor to rotate in a direction dependent upon the order of occurrence of the changes in the fine command and the fine feedback signals at a speed dependent upon the interval between the occurrence of the changes in the fine feedback and fine command signals.

Claim 4

A control circuit for comparing a coarse feedback signal and a fine feedback signal respectively with a coarse command signal and a fine command signal during each cycle of a reference wave and providing an error signal for controlling the speed of a motor in response to the difference in time of occurrence between a change from a first voltage level to a second voltage level of the feedback and the command signals and the direction of rotation of the motor in response to the order of occurrence of the voltage change of the feedback and the command signals, comprising: means including a bistable state coarse command flip flop having an input responsive to the change in the coarse command signal to condition the flip flop so the flip flop is switched from its ON to its OFF state by an input signal at its toggle and an input responsive to the change in the coarse feedback signal for maintaining the flip flop in its ON state, means including a bistable state coarse feedback flip flop having an input responsive to the change in the coarse feedback signal to condition the flip flop so the flip flop is switched from its ON to its OFF state by an input signal at its toggle and an input responsive to the change in the coarse command signal for maintaining the flip flop in its ON state, timing means including a bistable state timing flip flop having an input responsive to the changes in the coarse feedback signal and the coarse command signal and an output providing the output signals to the toggles of the coarse command flip flop and the coarse feedback flip flop for switching the conditioned coarse command flip flop or the coarse feedback flip flop from their ON to OFF states a predetermined time interval subsequent to the change in the coarse command signal or the coarse feedback signal respectively when the interval between the occurrence of the changes in the coarse command and the coarse feedback signals is greater than the predetermined interval and for maintaining the coarse command flip flop and the coarse feedback flip flops in their respective ON states when the interval between the occurrence of the changes in the coarse command and the coarse feedback signals is less than the predetermined interval, a first control means responsive to an output of the coarse command flip flop for energizing the motor for rotation in a first direction at a pre-determined speed when the coarse command flip flop is in its OFF state, a second control means responsive to an ouTput of the coarse feedback flip flop for energizing the motor for rotation in a direction opposite the first direction at a predetermined speed when the coarse feedback flip flop is in its OFF state, and a fine feedback and fine command signal comparison means operable when the coarse command and the coarse feedback flip flops are in their ON states and responsive to the fine command and fine feedback signals for respectively supplying the first and the second control means with input signals which will cause the motor to rotate in a direction dependent upon the order of occurrence of the changes in the fine command and the fine feedback signals at a speed dependent upon the interval between the occurrence of the changes in the fine feedback and fine command signals.

Claim 5

The control circuit as recited in claim 2 wherein the fine feedback and fine command signal comparison means includes: a first bistable state flip flop having a first input receiving the fine command signal and arranged to be switched from an ON state to an OFF state by the change in the fine command signal when a logic 1 signal is present at a second of its inputs and arranged to remain in its ON state when a logic 0 is present at its second input, a second bistable state flip flop having a first input receiving the fine feedback signal and arranged to be switched from its ON state to its OFF state by the change in the fine feedback signal when a logic 1 is present at a second of its inputs and arranged to remain in its ON state when a logic 0 is present at its second input, means responsive to the feedback signal for supplying the second input of the first flip flop with a logic 0 signal when the fine feedback signal is at the second voltage level and the second flip flop is in its ON state, means responsive to the fine command signal for supplying the second input of the second flip flop with a logic 0 signal when the fine command signal is at the second voltage level and the first flip flop is in its ON state, means responsive to an output of the first flip flop and supplying an input to the first control means for energizing the motor for rotation in the first direction when the first flip flop is in its OFF state, means responsive to an output of the second flip flop and supplying an input to the second control means for energizing the motor for rotation in the opposite direction when the second flip flop is in its OFF state, and means including a third flip flop responsive to an output of the first flip flop and an output of the second flip flop for switching the first and the second flip flops to their ON states when the first and the second flip flops are simultaneously in their OFF states.

Claim 6

A circuit for controlling the speed, direction of rotation and deceleration of an electric motor in response to a train of constant frequency pulses at each of two terminals with the pulses at the first of the two terminals appearing as a logic 1 pulse which changes from a logic 0 and progressively decreases from a constant width to zero to cause the motor rotation in a first direction to be decreased from a constant speed to zero and the pulses at a second of the two terminals appearing as a logic 0 pulse which changes from a logic 1 and progressively decreases from a constant width to zero to cause the motor rotation in a second direction that is the reverse of the first direction to decrease from a constant speed to zero, comprising: a capacitor, means controlled by the train of pulses at the two terminals for maintaining the capacitor in a discharged state when the first and the second terminals are simultaneously 0 and 1 respectively and when the first and the second terminals are simultaneously 1 and 0 respectively and for causing the capacitor to be charged in a first direction with a current flowing in a first direction during periods when the first and the second terminals are simultanEously 1 and for causing the capacitor to be charged in a second direction with a current flowing in a second direction during periods when the first and the second terminals are simultaneously 0, and means including an operational amplifier having an input responsive to the direction of flow of the charging current and the total current energy required to charge the capacitor in response to the pulses appearing at the first and second terminals and providing an output for causing the motor to rotate in the first direction in response to the direction of the charging current flow at a speed proportional to the total current energy required to charge the capacitor in the first direction and for causing the motor to rotate in the second direction in response to the direction of the charging current flow at a speed proportional to the total current energy required to charge the capacitor in the second direction.

Claim 7

A circuit for controlling the speed, direction of rotation and deceleration of an electric motor in response to a train of constant frequency pulses at each of two terminals with the pulses at the first of the two terminals appearing as a logic 1 pulse which changes from a logic 0 and progressively decreases from a constant width to zero to cause the motor rotation in a first direction to be decreased from a constant speed to zero and the pulses at a second of the two terminals appearing as a logic 0 pulse which changes from a logic 1 and progressively decreases from a constant width to zero to cause the motor rotation in a second direction that is the reverse of the first direction to decrease from a constant speed to zero, comprising: a capacitor, means controlled by the train of pulses at the two terminals for maintaining the capacitor in a discharged state when the first and the second terminals are simultaneously 0 and 1 respectively and when the first and the second terminals are simultaneously 1 and 0 respectively and for causing the capacitor to be charged in a first direction with a current flowing in a first direction during periods when the first and the second terminals are simultanEously 1 and for causing the capacitor to be charged in a second direction with a current flowing in a second direction during periods when the first and the second terminals are simultaneously 0, and means including an operational amplifier having an input responsive to the direction of flow of the charging current and the total current energy required to charge the capacitor in response to the pulses appearing at the first and second terminals and providing an output for causing the motor to rotate in the first direction in response to the direction of the charging current flow at a speed proportional to the total current energy required to charge the capacitor in the first direction and for causing the motor to rotate in the second direction in response to the direction of the charging current flow at a speed proportional to the total current energy required to charge the capacitor in the second direction.

Claim 8

The circuit as recited in claim 4 wherein the means for maintaining the capacitor in a discharged state and for causing the capacitor to be charged in a discharged state in response to the pulses at the two terminals includes: a junction, means including a pair of transistors respectively having their bases connected to the first and the second terminals for maintaining the junction at a common potential when the first and the second terminals are simultaneously 0 and 1 respectively and when the first and the second terminals are simultaneously 1 and 0 respectively and for causing the junction to have a first polarity during periods when the first and the second terminals are simultaneously 1 and a polarity opposite the first polarity when the first and second terminals are simultaneously 0, a means including a field effect transistor having a source and drain electrode connected across the capacitor and biased to a nonconductive state during periods when the first and second terminals are simultaneously 1 or 0, and means connecting the capacitor in a bidirectional charging circuit between the junction and the input of the operation amplifier.

Claim 9

The circuit as recited in claim 4 wherein the means for maintaining the capacitor in the discharged state and for causing the capacitor to be charged in response to the pulses at the two terminals includes a pnp type transistor and a npn type transistor, said transistors having their collectors respectively connected through load resistors to a negative voltage source and a positive voltage source, their emitters connected to a terminal that is common to the negative and the positive voltage sources, and their bases respectively connected to the first and the second terminals, a field effect transistor having its source and drain electrodes connected across the capacitor, and a gate electrode arranged to bias the field effect transistor against conduction when the gate electrode is negative in polarity relative to its source and drain electrodes, a first voltage divider having two opposite ends respectively connected to the collectors of the npn transistor and the pnp transistor and a junction intermediate the ends providing a voltage potential equal to one half the potential across the opposite ends, a second voltage divider having two opposite ends respectively connected between the collector of the npn type transistor and the negative polarity source and a junction providing a potential that is negative relative to the collector of the pnp transistor when the npn and the pnp transistors are conducting, a potential that is positive relative to the collector of the pnp transistor when the pnp and the npn transistors are nonconducting, a potential that is positive relative to the collector of the pnp transistor when the pnp transistor is nonconducting and the npn transistor is conducting and a potential that is positive relative to the collector of the pnp transistor when the npn transistor is nonconducting and the pnp transistor is conducting, a second pnp type tranSistor having an emitter connected to the collector of the pnp transistor, a base connected to the junction of the second voltage divider and a collector connected to the gate of the field effect transistor and the negative polarity source, and a capacitor charging circuit connecting a first side of the capacitor to the junction of the first voltage divider and a second side of the capacitor to an input of the operational amplifier, said charging circuit including a pair of reversely poled diodes connected to cause the capacitor to be charged with current flow in one direction when the npn transistor is nonconducting and the pnp transistor is conducting and with current flow in a direction opposite the said one direction when the pnp transistor is nonconducting and the npn transistor is conducting.