Relay release delay circuit

Claim 1

In combination with a relay: a source of energizing potential having a first polarity terminal and a second polarity terminal, said source being subject to voltage variations; a terminal of said relay operate winding connected to said first polarity terminal, operating means for operating said relay and connect means joining said operating means to another terminal of said relay, said operating means effective upon operation to apply a potential of said second polarity terminal to operate said relay, a relay release delay means having an input connected to said operating means and an output connected to said other terminal of said relay and comprising a first voltage divider, a first amplifier normally in a non-conductive state, said amplifier including first and second transistors each having a plurality of electrodes including an emitter, a collector and a base electrode, means for providing operating potentials to said electrodes for maintaining them in a normally non-conductive state, means for connecting said first transistor base to said operating means via said first voltage divider, said first and second transistors placed in a conductive state upon operation of said operate means, means connecting said second transistor base to said first transistor collector and other means connecting said second transistor collector to said relay other terminal whereby said relay is maintained in an operated condition during the conductive state of said transistors, a capacitor having a first plate connected to said second polarity terminal, and a second plate connected to an intermediate point of said voltage divider, a capacitor charging resistor connected from said first polarity voltage terminal to said first voltage divider intermediate point to maintain said capacitor in a charged state, a second voltage divider connected between said first polarity terminal and said second polarity terminal, a third transistor means providing operating potentials to said emitter and collector electrodes of said third transistor, said third transistor base electrode connected to the intermediate point of said second voltage divider and means including a blocking diode connecting said third transistor emitter through said blocking diode to said capacitor second plate to thereby maintain said capacitor at a charge level related to the voltage level of said energizing potential source.