US3732466A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmer
Assignee: Applied Automation Inc
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Filing: 1971-04-01
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Granted: 1973-05-08
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Expires: 1991-04-01
Abstract
Abstract A programmer is disclosed which utilizes a diode matrix. Pulses at a predetermined frequency are applied to the input of a counter which has a plurality of outputs. These outputs are applied to first terminals of the matrix so that signals are established representing consecutive time intervals. The matrix is provided with a plurality of outputs which are applied through latching circuits to provide control signals. The input and output terminals of the matrix are selectively connected together by means of diodes so that output signals are established in any desired time sequence. This programmer can be employed to advantage to control a chromatographic analyzer.
Inventors
- 👤 D Vesper
- 👤 V Street
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:37
CPC Classifications
G; G01; G01N; G01N30/00; G01N30/02; G01N30/88; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/08
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
237 words
A programmer comprising: counting means having an input and a plurality of outputs, said counting means being adapted to receive a plurality of input signals at a first frequency and to establish a plurality of output signals in response thereto at progressively later times after the first of the input signals is received; a plurality of output means; a plurality of control means, each having a first input to actuate the control means, a second input to deactuate the control means, and an output, each of said control means comprising a first latching means connected to the first input of said control means to establish an output signal after an input signal is received at said first input, a second latching means connected to the second input of said control means to establish an output signal after an input signal is received at said second input, and a driving means connected to the two latching means to provide an output actuating signal when an output signal is established by the first latching means and to provide a deactuating output signal when an output signal is established by the second latching means; means connecting the outputs of said control means to respective ones of said output means; and means to connect the outputs of said counting means selectively to the inputs of said control means so that said control means can be actuated and deactuated at selected times.
Claim 2
Dependent Claim
237 words
A programmer comprising: counting means having an input and a plurality of outputs, said counting means being adapted to receive a plurality of input signals at a first frequency and to establish a plurality of output signals in response thereto at progressively later times after the first of the input signals is received; a plurality of output means; a plurality of control means, each having a first input to actuate the control means, a second input to deactuate the control means, and an output, each of said control means comprising a first latching means connected to the first input of said control means to establish an output signal after an input signal is received at said first input, a second latching means connected to the second input of said control means to establish an output signal after an input signal is received at said second input, and a driving means connected to the two latching means to provide an output actuating signal when an output signal is established by the first latching means and to provide a deactuating output signal when an output signal is established by the second latching means; means connecting the outputs of said control means to respective ones of said output means; and means to connect the outputs of said counting means selectively to the inputs of said control means so that said control means can be actuated and deactuated at selected times.
Claim 3
Dependent Claim
47 words
The programmer of claim 1, further comprising reset means having an input and an output, the output of said reset means being connected to each of said latching means, and means to connect the input of said reset means selectively to the outputs of said counting means.
Claim 4
Dependent Claim
34 words
The programmer of claim 2 wherein said reset means includes a delay means to delay the application of reset signals to said latching means after an input signal is applied to said reset means.
Claim 5
Dependent Claim
89 words
The programmer of claim 1, further comprising an additional output means, and an additional control means having an input and an output, means to connect the outputs of said counting means selectively to the input of said additional control means, and means to connect the output of said additional control means to said additional output means, said additional control means having a delay therein to permit said additional output means to be actuated for a predetermined time interval after an input signal is applied to said additional control means.
Claim 6
Dependent Claim
15 words
The programmer of claim 1 wherein said means to connect comprise a plurality of diodes.
Claim 7
Dependent Claim
165 words
ThE programmer of claim 1 wherein each of said control means comprises first and second inverters, the inputs of which are adapted to receive input signals; a third inverter having its input connected to the output of said first inverter; a fourth inverter having its input connected to the output of said second inverter; first, second and third NAND gates, each having first and second inputs; means connecting the outputs of said third inverter and said second inverter to the respective inputs of said first gate; means connecting the output of said third inverter to the first input of said second gate; means connecting the output of said second gate to the input of said third inverter; means connecting the output of said fourth inverter to the first input of said third gate; and means connecting the output of said third gate to the input of said fourth inverter; the second inputs of said second and third gates being adapted to receive a reset signal.
Claim 8
Dependent Claim
51 words
The programmer of claim 6, further comprising reset means having an input and an output, means to connect the input of said reset means selectively to the outputs of said counting means, and means connecting the output of said reset means to the second inputs of said second and third gates.
References Cited (Backward Citations)
US3391305A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-07 | 1976-11-06 | 1977-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-07 | 1980-11-06 | 1981-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-07 | 1984-11-06 | 1985-05-08 | $7700.00 | Window Closed / Lapsed |