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US3732408A Expired / Lapsed US ⏱️ 0.0 years remaining

Output device for electronic data processing systems

Assignee: Olympia Werke AG
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Filing: 1971-03-16
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Granted: 1973-05-08
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Expires: 1991-03-16
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Abstract

Abstract In a system for converting binary data into a decimal readout and in which the bits of a succession of binary words are fed in series into a shift register and fed out therefrom in parallel to control the selection of each decimal digit of the readout, a circuit for controlling the insertion of a decimal point at a selected location of the decimal readout by the application of a signal to a selected one of a plurality of selection inputs each corresponding to a respective location of the decimal readout, the circuit applying an additional shift pulse to the shift register for preventing the storage of a data bit in the shift register location corresponding to the selected decimal readout location and triggering the insertion of a decimal point at the selected readout location.

Inventors

  • 👤 H Bettin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 21:21
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/02; G06F15/0225

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 524 words
For use in an electronic data processing system each reaDout of which is displayed in the form of a sequence of characters and a given symbol at a series of readout locations, the system providing, for each such readout, a series of data words representative of such readout and each composed of a plurality of bits, and a selection signal identifying the readout location at which the given symbol is to be inserted, the system including a shift register having a plurality of stages and connected to receive each data word in sequence, the bits of each data word being fed in series into the register, a readout character selection control device connected to the shift register to permit the bits of each data word in the register to be transferred in parallel into the control device, a readout device connected to the control device and presenting the readout locations, and a source of clock pulses having a given repetition rate, the source being connected to the shift register to cause the bits of each successive data word to be shifted from one register stage to the next at such given rate, the improvement composed of a symbol insertion control circuit, comprising in combination: a plurality of location selection inputs each corresponding to a respective one of the readout locations at which the given symbol may be inserted, said inputs being connected to the system for causing the selection signal for each readout to be applied only to that one input which corresponds to the readout location at which the given symbol is to be inserted; a pulse controlled counter having a plurality of stages equal in number to said plurality of inputs and connected to receive a series of pulses occurring at the given rate and to shift such pulses from one stage thereof to the next at such rate, said pulses received by said counter bearing a phase relation to the clock pulses such as to cause the extra shift pulse to be produced between two successive clock pulses, thereby reserving a readout location in storage for the given symbol, which location is the same for each data word associated with a single readout; a sequencing unit having a plurality of pairs of inputs, one input of each pair being connected to a respective location selection input and the other input of each pair being connected to a respective counter stage, said sequencing unit including logic means connected to each pair of inputs for producing an output signal when a pulse appears at that counter stage which is connected to same pair of inputs as that selection input to which the selection signal is applied; means connecting said logic means to the shift register for causing the output signal from said logic means to apply an extra shift pulse to the register during the feed in of each data word thereto; and means effectively connecting each said selection input to that portion of the character selection control device associated with its corresponding readout location for causing the selection signal to effect the insertion of the given symbol at the selected readout location.
Claim 2
Dependent Claim 524 words
For use in an electronic data processing system each reaDout of which is displayed in the form of a sequence of characters and a given symbol at a series of readout locations, the system providing, for each such readout, a series of data words representative of such readout and each composed of a plurality of bits, and a selection signal identifying the readout location at which the given symbol is to be inserted, the system including a shift register having a plurality of stages and connected to receive each data word in sequence, the bits of each data word being fed in series into the register, a readout character selection control device connected to the shift register to permit the bits of each data word in the register to be transferred in parallel into the control device, a readout device connected to the control device and presenting the readout locations, and a source of clock pulses having a given repetition rate, the source being connected to the shift register to cause the bits of each successive data word to be shifted from one register stage to the next at such given rate, the improvement composed of a symbol insertion control circuit, comprising in combination: a plurality of location selection inputs each corresponding to a respective one of the readout locations at which the given symbol may be inserted, said inputs being connected to the system for causing the selection signal for each readout to be applied only to that one input which corresponds to the readout location at which the given symbol is to be inserted; a pulse controlled counter having a plurality of stages equal in number to said plurality of inputs and connected to receive a series of pulses occurring at the given rate and to shift such pulses from one stage thereof to the next at such rate, said pulses received by said counter bearing a phase relation to the clock pulses such as to cause the extra shift pulse to be produced between two successive clock pulses, thereby reserving a readout location in storage for the given symbol, which location is the same for each data word associated with a single readout; a sequencing unit having a plurality of pairs of inputs, one input of each pair being connected to a respective location selection input and the other input of each pair being connected to a respective counter stage, said sequencing unit including logic means connected to each pair of inputs for producing an output signal when a pulse appears at that counter stage which is connected to same pair of inputs as that selection input to which the selection signal is applied; means connecting said logic means to the shift register for causing the output signal from said logic means to apply an extra shift pulse to the register during the feed in of each data word thereto; and means effectively connecting each said selection input to that portion of the character selection control device associated with its corresponding readout location for causing the selection signal to effect the insertion of the given symbol at the selected readout location.
Claim 3
Dependent Claim 62 words
An arrangement as defined in claim 1, further comprising a plurality of electronic switches in the form of thyristors forming part of the character selection control device, each thyristor being connected to the readout device to control the output at a selected location in the readout and to be actuated by a signal on the selection input associated with its respective location.
Claim 4
Dependent Claim 47 words
An arrangement as defined in claim 2, further comprising a pulse generator connected to said counter for producing the pulses which control said counter, said generator producing pulses at a rate equal to the rate at which signals are shifted through the stages of the shift register.
Claim 5
Dependent Claim 46 words
An arrangement as defined in claim 3, wherein said sequencing unit comprises a group of AND circuits each having two inputs constituting a respective pair of inputs, and an OR circuit having a plurality of inputs each connected to the output of a respective AND circuit.
Claim 6
Dependent Claim 77 words
An arrangement as defined in clAim 4, wherein said means connecting each selection input to the character selection control device comprise: a second group of AND circuits each having one input connected to a respective selection input and a second input connected to a common signal line which provides a gating signal indicating the readiness of the readout device to insert the given symbol, each AND circuit having an output connected to actuate a respective electronic switch.

References Cited (Backward Citations)

US3384009A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-05-07 1976-11-06 1977-05-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-05-07 1980-11-06 1981-05-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-05-07 1984-11-06 1985-05-08 $7700.00 Window Closed / Lapsed

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