US3729676A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ratemeter
Assignee: National Aeronautics and Space Administration
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Filing: 1971-07-13
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Granted: 1973-04-24
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Expires: 1991-07-13
Abstract
Abstract An instantaneous reading tachometer in which reoccurring events to be measured in rate, trigger a three-state timing generator in which the first two states are of fixed duration and the third state is of variable duration. An electrical decay circuit is set to a reference level by the second state and the third state causes this reference level to decay until the re-occurrence of an event. This triggers a new first state which in turn triggers a sample and hold circuit to hold the decayed level. The decayed level is amplified and provided as an output indicative of the instantaneous rate of occurrence of the last two successive events.
Inventors
- 👤 J Currie
- 👤 R Kissell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:42
CPC Classifications
A; A61; A61B; A61B5/00; A61B5/02; A61B5/024; A61B5/0245; G; G01; G01R; G01R23/00; G01R23/02
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
607 words
A ratemeter comprising: A. sensing means responsive to re-occurring events, for providing an electrical output, timing, pulse of a first polarity upon the occurrence of each event; B. timing means responsive to each said output pulse of said sensing means for providing, successively, and on a reoccurring basis, first, second and third discrete electrical levels, said first and second electrical levels being of predetermined duration and the duration of said third level being equal to the period between said output pulses less the total duration of said first and second electrical levels, and wherein said timing means comprises: 1. a differential amplifier having a first input, a second input and an output, said first input and said output being of like phase and said second input being of opposite phase to that of said output, 2. first circuit means connecting a portion of the output voltage present on said output to said first input and including first switching means connected to said first input and responsive to a second polarity output of said amplifier for shorting said first input, 3. second circuit means comprising: a capacitor having one terminal connected to a reference potential, a resistor connected between the other terminal of said capacitor and said second input, a circuit connecting said output through said resistor to said capacitor, and second switching means connected across said resistor and responsive to a second polarity output of said amplifier for shorting said resistor between said capacitor and said second input, whereby with an initial condition of zero voltage on said inputs there exists a zero voltage as said third discrete electrical level on said output, a said first polarity timing pulse applied to said first input causes said amplifier to provide a maximum first polarity output, or first discrete electrical level, which output is coupled to said capacitor which commences charging in a first polarity direction to provide an increasing amplitude first polarity input to said second input and timing the duration of said first discrete electrical level, when the level of said first polarity voltage on said second input exceeds the level on said first input the differential input of said amplifier switches polarity and the potential on said output changes to a maximum second polarity value as said second discrete electrical level, and said second switching means is operated by said second polarity from said output shorting said resistor and causing said capacitor to commence discharging, timing said second discrete electrical level, and when the voltage on said second input is pulled down to a point which causes the differential amplifier to abruptly change from said second electrical discrete level to a neutral state with a zero output, said third discrete electrical level is provided on said output, which level remains until the re-occurrence of a said timing pulse; C. decay circuit means responsive to the output of said timing means and to the initiation of said second electrical level for establishing a reference voltage and including time constant means responsive to the initiation of said third level for providing a voltage which initially corresponds to said reference voltage, then decays during said third electrical level to a decayed level, and including means responsive to the next occurring said first electrical level for halting said decay and holding the decayed level for the duration of said next occurring first electrical level; and D. sample and hold means responsive to said decay circuit means and said decayed level for providing a substantially continuously level output proportional to the last held decayed level and which is representative of the rate of occurrence of the last two successive said events.
Claim 2
Dependent Claim
607 words
A ratemeter comprising: A. sensing means responsive to re-occurring events, for providing an electrical output, timing, pulse of a first polarity upon the occurrence of each event; B. timing means responsive to each said output pulse of said sensing means for providing, successively, and on a reoccurring basis, first, second and third discrete electrical levels, said first and second electrical levels being of predetermined duration and the duration of said third level being equal to the period between said output pulses less the total duration of said first and second electrical levels, and wherein said timing means comprises: 1. a differential amplifier having a first input, a second input and an output, said first input and said output being of like phase and said second input being of opposite phase to that of said output, 2. first circuit means connecting a portion of the output voltage present on said output to said first input and including first switching means connected to said first input and responsive to a second polarity output of said amplifier for shorting said first input, 3. second circuit means comprising: a capacitor having one terminal connected to a reference potential, a resistor connected between the other terminal of said capacitor and said second input, a circuit connecting said output through said resistor to said capacitor, and second switching means connected across said resistor and responsive to a second polarity output of said amplifier for shorting said resistor between said capacitor and said second input, whereby with an initial condition of zero voltage on said inputs there exists a zero voltage as said third discrete electrical level on said output, a said first polarity timing pulse applied to said first input causes said amplifier to provide a maximum first polarity output, or first discrete electrical level, which output is coupled to said capacitor which commences charging in a first polarity direction to provide an increasing amplitude first polarity input to said second input and timing the duration of said first discrete electrical level, when the level of said first polarity voltage on said second input exceeds the level on said first input the differential input of said amplifier switches polarity and the potential on said output changes to a maximum second polarity value as said second discrete electrical level, and said second switching means is operated by said second polarity from said output shorting said resistor and causing said capacitor to commence discharging, timing said second discrete electrical level, and when the voltage on said second input is pulled down to a point which causes the differential amplifier to abruptly change from said second electrical discrete level to a neutral state with a zero output, said third discrete electrical level is provided on said output, which level remains until the re-occurrence of a said timing pulse; C. decay circuit means responsive to the output of said timing means and to the initiation of said second electrical level for establishing a reference voltage and including time constant means responsive to the initiation of said third level for providing a voltage which initially corresponds to said reference voltage, then decays during said third electrical level to a decayed level, and including means responsive to the next occurring said first electrical level for halting said decay and holding the decayed level for the duration of said next occurring first electrical level; and D. sample and hold means responsive to said decay circuit means and said decayed level for providing a substantially continuously level output proportional to the last held decayed level and which is representative of the rate of occurrence of the last two successive said events.
Claim 3
Dependent Claim
43 words
first circuit means connecting a portion of the output voltage present on said output to said first input and including first switching means connected to said first input and responsive to a second polarity output of said amplifier for shorting said first input,
Claim 4
Dependent Claim
43 words
first circuit means connecting a portion of the output voltage present on said output to said first input and including first switching means connected to said first input and responsive to a second polarity output of said amplifier for shorting said first input,
Claim 5
Dependent Claim
36 words
A ratemeter as set forth in claim 1 wherein the duration of said first electrical level is between 1 and 2000 milliseconds and the duration of said second electrical level is between 1 and 2000 milliseconds.
Claim 6
Dependent Claim
38 words
A ratemeter as set forth in claim 1 wherein said first electrical level is of a positive potential, said second electrical level is of a negative potential and said third electrical level is of a zero electrical potential.
Claim 7
Dependent Claim
427 words
second circuit means comprising: a capacitor having one terminal connected to a reference potential, a resistor connected between the other terminal of said capacitor and said second input, a circuit connecting said output through said resistor to said capacitor, and second switching means connected across said resistor and responsive to a second polarity output of said amplifier for shorting said resistor between said capacitor and said second input, whereby with an initial condition of zero voltage on said inputs there exists a zero voltage as said third discrete electrical level on said output, a said first polarity timing pulse applied to said first input causes said amplifier to provide a maximum first polarity output, or first discrete electrical level, which output is coupled to said capacitor which commences charging in a first polarity direction to provide an increasing amplitude first polarity input to said second input and timing the duration of said first discrete electrical level, when the level of said first polarity voltage on said second input exceeds the level on said first input the differential input of said amplifier switches polarity and the potential on said output changes to a maximum second polarity value as said second discrete electrical level, and said second switching means is operated by said second polarity from said output shorting said resistor and causing said capacitor to commence discharging, timing said second discrete electrical level, and when the voltage on said second input is pulled down to a point which causes the differential amplifier to abruptly change from said second electrical discrete level to a neutral state with a zero output, said third discrete electrical level is provided on said output, which level remains until the re-occurrence of a said timing pulse; C. decay circuit means responsive to the output of said timing means and to the initiation of said second electrical level for establishing a reference voltage and including time constant means responsive to the initiation of said third level for providing a voltage which initially corresponds to said reference voltage, then decays during said third electrical level to a decayed level, and including means responsive to the next occurring said first electrical level for halting said decay and holding the decayed level for the duration of said next occurring first electrical level; and D. sample and hold means responsive to said decay circuit means and said decayed level for providing a substantially continuously level output proportional to the last held decayed level and which is representative of the rate of occurrence of the last two successive said events.
Claim 8
Dependent Claim
427 words
second circuit means comprising: a capacitor having one terminal connected to a reference potential, a resistor connected between the other terminal of said capacitor and said second input, a circuit connecting said output through said resistor to said capacitor, and second switching means connected across said resistor and responsive to a second polarity output of said amplifier for shorting said resistor between said capacitor and said second input, whereby with an initial condition of zero voltage on said inputs there exists a zero voltage as said third discrete electrical level on said output, a said first polarity timing pulse applied to said first input causes said amplifier to provide a maximum first polarity output, or first discrete electrical level, which output is coupled to said capacitor which commences charging in a first polarity direction to provide an increasing amplitude first polarity input to said second input and timing the duration of said first discrete electrical level, when the level of said first polarity voltage on said second input exceeds the level on said first input the differential input of said amplifier switches polarity and the potential on said output changes to a maximum second polarity value as said second discrete electrical level, and said second switching means is operated by said second polarity from said output shorting said resistor and causing said capacitor to commence discharging, timing said second discrete electrical level, and when the voltage on said second input is pulled down to a point which causes the differential amplifier to abruptly change from said second electrical discrete level to a neutral state with a zero output, said third discrete electrical level is provided on said output, which level remains until the re-occurrence of a said timing pulse; C. decay circuit means responsive to the output of said timing means and to the initiation of said second electrical level for establishing a reference voltage and including time constant means responsive to the initiation of said third level for providing a voltage which initially corresponds to said reference voltage, then decays during said third electrical level to a decayed level, and including means responsive to the next occurring said first electrical level for halting said decay and holding the decayed level for the duration of said next occurring first electrical level; and D. sample and hold means responsive to said decay circuit means and said decayed level for providing a substantially continuously level output proportional to the last held decayed level and which is representative of the rate of occurrence of the last two successive said events.
Claim 9
Dependent Claim
42 words
A ratemeter as set forth in claim 1 wherein said decay circuit means comprises means for providing an output which is equal to said decayed level during said first electrical level and is substantially zero during said second and third electrical levels.
References Cited (Backward Citations)
US3599627A
Cited
US3614634A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-23 | 1976-10-23 | 1977-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-23 | 1980-10-23 | 1981-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-23 | 1984-10-23 | 1985-04-24 | $7700.00 | Window Closed / Lapsed |