Digital signal decoder using two reference waves

Claim 2

A decoder for an information signal in which a transition occurs at the center of a bit cell containing a ''''1,'''' and a transition may occur at the boundary between two successive bit cells containing ''''0''''s, whereby a ''''0'''' is represented by a half cycle of a wave having a 0* phase or a 180* phase, and a ''''1'''' is represented by a half cycle of a wave having a 90* phase or a 270* phase, comprising a first synchronous demodulator receptive to said information signal and a first reference wave, a second synchronous demodulator receptive to said information signal and a second reference wave, said first and second reference waves having a half cycle equal in duration to a bit cell of said information signal, having a quadrature phase relation with each other, and having 45* phase displacements relative to said phases of said information signal, and comparison logic means responsive to the outputs of said demodulators to generate an NRZ output signal.

Claim 3

A decoder as defined in claim 1 wherein said synchronous demodulators are each constituted by a multiplier.

Claim 4

A decoder as defined in claim 2 wherein said demodulators each include a low-pass filter following the multiplier.

Claim 5

A decoder as defined in claim 3 wherein said demodulators each include a limiter following the low-pass filter.

Claim 6

A decoder as defined in claim 1 wherein said means responsive to the outputs of the demodulators includes means to delay the output of one demodulator an amount equal to half a bit cell.

Claim 7

A decoder as defined in claim 1 and, in addition, timing means to derive said reference waves from said information signal.

Claim 8

A decoder as defined in claim 6 wherein said timing means includes means to derive a clock pulse wave from said information signal, and means responsive to the outputs of said demodulators to automatically correct the phase of the clock pulse wave if it is 180* out of the correct phase.

Claim 9

A decoder as defined in claim 1 wherein said first reference wave has a 45* phase, and said second reference wave has a 135* phase, and wherein said comparison logic means generate a ''''1'''' level when the outputs of the two demodulators have the same polarity, and generate a ''''0'''' level when the outputs have different polarities.

Claim 10

A decoder for an information signal in which a transition occurs at the center of a bit cell containing a ''''1,'''' and a transition may occur at the boundary between two successive bit cells containing ''''0''''s, whereby a ''''0'''' is represented by a half cycle of a wave having a 0* phase or a 180* phase, and a ''''1'''' is represented by a half cycle of a wave having a 90* phase or a 270* phase, comprising a 45* synchronous demodulator receptive to said information signal and a reference wave having a 45* phase, whereby the output of the demodulator is positive for a ''''0'''' bit having 0* phase and is negative for a ''''0'''' bit having a 180* phase, a 135* synchronous demodulator receptive to said information signal and a reference wave having a 135* phase, whereby the output of the demodulator is positive for a ''''1'''' bit having a 90* phase and is negative for a ''''1'''' bit having a 270* phase, and means responsive to the outputs of the demodulators to generate an NRZ output signal having a ''''1'''' level when the outputs of the two demodulators have the same polarity, and having a ''''0'''' level when the outputs have different polarities.

Claim 11

A decoder for an information signal in which a transition occurs at the center of a bit cell containing a ''''1,'''' and a transition may occur at the boundary between two successive bit cells containing ''''0''''s, whereby a ''''0'''' is represented by a half cycle of a wave having a 0* phase or a 180* phase, and a ''''1'''' is represented by a half cycle of a wave having a 90* phase or a 270* phase, comprising a 45* synchronous demodulator receptive to said information signal and a reference wave having a 45* phase, whereby the output of the demodulator is positive for a ''''0'''' bit having 0* phase and is negative for a ''''0'''' bit having a 180* phase, a 135* synchronous demodulator receptive to said information signal and a reference wave having a 135* phase, whereby the output of the demodulator is positive for a ''''1'''' bit having a 90* phase and is negative for a ''''1'''' bit having a 270* phase, and means responsive to the outputs of the demodulators to generate an NRZ output signal having a ''''1'''' level when the outputs of the two demodulators have the same polarity, and having a ''''0'''' level when the outputs have different polarities.