Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
191 words
An apparatus for adjusting the time relationship between data bits in plural channels in a communications system of the type having at least two channels for the parallel transmission of the data bits and wherein one channel is designated as a master channel and each other channel is a slave channel, the apparatus comprising the combination of means in the master channel for generating a delayed data bit output signal a predetermined time after receipt of a data bit input signal; means responsive to a signal from the master channel for generating signals defining an interval symmetrically located about the data bit output signal of the master unit; means in the slave channel for generating a delayed data bit output signal a predetermined time after receipt of a data bit input signal; means responsive to said means for generating signals defining an interval for determining the existence of said slave channel data bit output signal outside of said interval for generating a control signal indicative of said existence and means responsive to said control signal for altering said predetermined delay in the slave channel for the next data bit output signal.
Claim 2
Independent Claim
191 words
An apparatus for adjusting the time relationship between data bits in plural channels in a communications system of the type having at least two channels for the parallel transmission of the data bits and wherein one channel is designated as a master channel and each other channel is a slave channel, the apparatus comprising the combination of means in the master channel for generating a delayed data bit output signal a predetermined time after receipt of a data bit input signal; means responsive to a signal from the master channel for generating signals defining an interval symmetrically located about the data bit output signal of the master unit; means in the slave channel for generating a delayed data bit output signal a predetermined time after receipt of a data bit input signal; means responsive to said means for generating signals defining an interval for determining the existence of said slave channel data bit output signal outside of said interval for generating a control signal indicative of said existence and means responsive to said control signal for altering said predetermined delay in the slave channel for the next data bit output signal.
Claim 3
Dependent Claim
43 words
An apparatus according to claim 1 and wherein said means for generating signals defining an interval further comprises means for adjusting the time duration of said interval to adjust the sensitivity of said means for altering said predetermined delay in the slave channel.
Claim 4
Dependent Claim
69 words
An apparatus according to claim 1 wherein said means for generating signals defining an interval further comprises means for adjusting the time duration of said interval to adjust the sensitivity of said means for altering said predetermined delay in the slave channel and means responsive to said control signal from said means for altering said predetermined delay in the slave channel for automatically adjusting the duration of said interval.
Claim 5
Independent Claim
262 words
An apparatus for adjusting the time relationship between data bits in plural channels in a communications system of the type having at least two channels for the parallel transmission of the data bits and wherein one channel is designated as a master channel and each other channel is a slave channel, the apparatus comprising the combination of means in the master channel for generating a delayed data bit output signal a predetermined time after receipt of a data bit input signal; means responsive to a signal from the master channel for generating an early gate signal having a trailing edge; means responsive to a signal from the master channel for generating a late gate signal having a leading edge spaced in time after said trailing edge; means in said slave channel for generating a delayed data bit output signal a predetermined time after receipt of a data bit input signal; means in the slave channel responsive to said trailing and leading edges of said early and late gate signals, respectively, for defining an interval within which the delayed data bit output signal from said slave channel is to be produced to be in substantial time coincidence with the delayed data bit in said master channel; means responsive to said means for defining an interval for determining the existence of said slave channel data bit output signal outside of said interval for generating a control signal indicative of said existence and means responsive to said control signal for altering said predetermined delay in said slave channel for the next data bit output signal.
Claim 6
Independent Claim
262 words
An apparatus for adjusting the time relationship between data bits in plural channels in a communications system of the type having at least two channels for the parallel transmission of the data bits and wherein one channel is designated as a master channel and each other channel is a slave channel, the apparatus comprising the combination of means in the master channel for generating a delayed data bit output signal a predetermined time after receipt of a data bit input signal; means responsive to a signal from the master channel for generating an early gate signal having a trailing edge; means responsive to a signal from the master channel for generating a late gate signal having a leading edge spaced in time after said trailing edge; means in said slave channel for generating a delayed data bit output signal a predetermined time after receipt of a data bit input signal; means in the slave channel responsive to said trailing and leading edges of said early and late gate signals, respectively, for defining an interval within which the delayed data bit output signal from said slave channel is to be produced to be in substantial time coincidence with the delayed data bit in said master channel; means responsive to said means for defining an interval for determining the existence of said slave channel data bit output signal outside of said interval for generating a control signal indicative of said existence and means responsive to said control signal for altering said predetermined delay in said slave channel for the next data bit output signal.
Claim 7
Dependent Claim
34 words
An apparatus according to claim 4 and further comprising means for adjusting the time spacing between said trailing edge and said leading edge to adjust the sensitivity of said means in said slave channel.
Claim 8
Dependent Claim
37 words
An apparatus according to claim 5 and further comprising means responsive to signals from said means for altering said predetermined delay in said slaVe channel for automatically adjusting the duration of said early and late gate signals.
Claim 9
Dependent Claim
54 words
An apparatus according to claim 4 wherein said means in the master channel includes an oscillator; a counter connected to count output signals from said oscillator commencing with the arrival of said data bit input signal; and a comparator for generating a delayed data bit output signal when said counter reaches a predetermined count.
Claim 10
Dependent Claim
80 words
An apparatus according to claim 7 wherein said means for generating an early gate signal includes a bi-stable circuit responsive to the arrival of a data bit input signal on said master channel to initiate said early gate signal; a second comparator connected to said counter; means for providing a predetermined input to said comparator, said comparator being operative to trigger said bi-stable circuit to terminate said early gate signal when the count in said counter equals said predetermined input.
Claim 11
Dependent Claim
20 words
An apparatus according to claim 8 wherein said predetermined input is changeable to alter the duration of said early gate.
Claim 12
Dependent Claim
86 words
An apparatus according to claim 8 wherein said means for generating a late gate signal includes a third comparator circuit connected to said counter; means for providing the complement of said predetermined input to said third comparator, a bi-stable circuit responsive to the arrival of the count in said counter at a level of said complement input to initiate generation of said late gate signal, said bi-stable circuit being responsive to the arrival of said counter at a second predetermined count to terminate said late gate.