US3728529A
Expired / Lapsed
US
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Two-way communication system employing two-clock frequency pseudo-noise signal modulation
Assignee: Unisys Corp
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Filing: 1971-12-17
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Granted: 1973-04-17
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Expires: 1991-12-17
Abstract
Abstract A digital two-way communication system utilizing RF transmissions that are phase-shift-keyed (PSK) by binary pseudonoise (PN) code generators operating at different clock rates. Transmissions in the first and second directions are modulated by composite PN code generators operating at different first and second clock frequencies f1 and f2, respectively, where f1 NF2, with N being a positive integer having no factors in common with the lengths of the component PN coder from which the composite is formed. The binary digital data signals that are to be transmitted in either direction modulate a binary PN code which is a composite code generated from a plurality of component PN codes. Each of these data-modulated composite PN codes, which are generated at clock frequencies f1 and f2, respectively, modulates, in turn, an RF carrier signal. By having the two communication stations transmit and receive at different PN clock frequencies, equipment limitations that restrict transmitter performance in the second direction need not limit performance in the first direction, thereby allowing a higher clock frequency f1, in the first direction and subsequent lower power required at the receiver at the other end for the same SNR out of the receiver.
Inventors
- 👤 E Kartchner
- 👤 Horn G Van
- 👤 R Wallace
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:18
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/14; H04L5/143
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
296 words
A two clock-frequency PN generator, comprising: a plurality of A, B - - K of PN component code generators for generating an associated plurality of A, B, - - K PN component codes of associated different lengths LA, LB, - - LK; a first clock generator for generating a first clock signal of a frequency f1; a second clock generator for generating a second clock signal of a frequency f2, where f1 Nf2 with N being a positive integer relatively prime to code lengths LA, LB, - - - LK; means for coupling said first clock signal of frequency f1 to said plurality of A, B, - - K PN component code generators for generating said plurality of A, B, - - K PN component codes at said PN bit frequency f1; a sampling device; means coupling said plurality of A, B, - - K PN component codes to said sampling device, and means coupling said second clock signal of frequency f2 to said sampling device for causing said sampling device to generate a plurality of PN component codes A'', B'', - - K'' of associated different lengths LA , LB , - - LK ; first code combiner means; means coupling said plurality of A'', B'', - - K'' PN component codes to said first code combiner means for generating a PN composite code X'' of a PN bit frequency f2 and of a length LX'' (LA'') (LB'') - - (LK''), the product of the component code lengths; second code combiner means; means coupling said plurality of A, B, - - K PN component codes to said second code combiner means for generating a second PN composite code X of a PN bit frequency f1 and of a length LX (LA) (LB) - - (LK);
Claim 2
Dependent Claim
296 words
A two clock-frequency PN generator, comprising: a plurality of A, B - - K of PN component code generators for generating an associated plurality of A, B, - - K PN component codes of associated different lengths LA, LB, - - LK; a first clock generator for generating a first clock signal of a frequency f1; a second clock generator for generating a second clock signal of a frequency f2, where f1 Nf2 with N being a positive integer relatively prime to code lengths LA, LB, - - - LK; means for coupling said first clock signal of frequency f1 to said plurality of A, B, - - K PN component code generators for generating said plurality of A, B, - - K PN component codes at said PN bit frequency f1; a sampling device; means coupling said plurality of A, B, - - K PN component codes to said sampling device, and means coupling said second clock signal of frequency f2 to said sampling device for causing said sampling device to generate a plurality of PN component codes A'', B'', - - K'' of associated different lengths LA , LB , - - LK ; first code combiner means; means coupling said plurality of A'', B'', - - K'' PN component codes to said first code combiner means for generating a PN composite code X'' of a PN bit frequency f2 and of a length LX'' (LA'') (LB'') - - (LK''), the product of the component code lengths; second code combiner means; means coupling said plurality of A, B, - - K PN component codes to said second code combiner means for generating a second PN composite code X of a PN bit frequency f1 and of a length LX (LA) (LB) - - (LK);
Claim 3
Dependent Claim
302 words
A two clock-frequency PN generator, comprising: a plurality of A, B, - - K of PN component code generators for generating an associated plurality of A, B, - - K PN component codes of associated different lengths LA, LB - - LK; a first clock generator for generating a first clock signal of a frequency f1; a second clock generator for generating a second clock signal of a frequency f2, where f1 Nf2 with N being a positive integer relatively prime to code lengths LA, LB, - - LK; means for coupling said first clock signal of frequency f1 to said plurality of A, B, - - K PN component code generators for generating said plurality of A, B, - - K PN component codes at said PN bit frequency f1; a sampling device; means coupling said plurality of A, B, - - K PN component codes to said sampling device, and means coupling said second clock signal of frequency f2 to said sampling device for causing said sampling device to generate a plurality of A'', B'', - - K'' PN component codes of associated different lengths LA , LB , - - LK ; MAJ'' code combiner means; means coupling said plurality of A'', B'', - - K'' PN component codes to said MAJ'' code combiner means for generating corresponding MAJ'' PN composite code of a PN bit frequency f2 AND of length (LA'') (LB'') - - (LK''), the product of the lengths of the component codes; MAJ code combiner means; means coupling said plurality of A, B, - - K PN component codes to said MAJ code combiner means for generating corresponding MAJ PN composite codes of a PN bit frequency f1 and of a length (LA) (LB) - - (LK), the product of the lengths of the component codes.
Claim 4
Dependent Claim
302 words
A two clock-frequency PN generator, comprising: a plurality of A, B, - - K of PN component code generators for generating an associated plurality of A, B, - - K PN component codes of associated different lengths LA, LB - - LK; a first clock generator for generating a first clock signal of a frequency f1; a second clock generator for generating a second clock signal of a frequency f2, where f1 Nf2 with N being a positive integer relatively prime to code lengths LA, LB, - - LK; means for coupling said first clock signal of frequency f1 to said plurality of A, B, - - K PN component code generators for generating said plurality of A, B, - - K PN component codes at said PN bit frequency f1; a sampling device; means coupling said plurality of A, B, - - K PN component codes to said sampling device, and means coupling said second clock signal of frequency f2 to said sampling device for causing said sampling device to generate a plurality of A'', B'', - - K'' PN component codes of associated different lengths LA , LB , - - LK ; MAJ'' code combiner means; means coupling said plurality of A'', B'', - - K'' PN component codes to said MAJ'' code combiner means for generating corresponding MAJ'' PN composite code of a PN bit frequency f2 AND of length (LA'') (LB'') - - (LK''), the product of the lengths of the component codes; MAJ code combiner means; means coupling said plurality of A, B, - - K PN component codes to said MAJ code combiner means for generating corresponding MAJ PN composite codes of a PN bit frequency f1 and of a length (LA) (LB) - - (LK), the product of the lengths of the component codes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-16 | 1976-10-16 | 1977-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-16 | 1980-10-16 | 1981-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-16 | 1984-10-16 | 1985-04-17 | $7700.00 | Window Closed / Lapsed |