Counter anti-jitter circuit

Claim 2

A digital counter characterized by reduced jitter in the output thereof comprising input circuit means for receiving input signals to be counted, and for producing first signals representative of the input signals, digital counting means for counting phase modified signals applied thereto over a given time base period and providing a readout thereof, time base and control means for providing a time base signal, independent of the input signals and for applying the phase modified signals to said digital counting means, fractional count detector means coupled with said digital counting means for receiving the first signals from said input circuit means and for detecting the value of a fractional count occurring during the time base period of said time base and control means, fractional count modifier means for combining the fractional count from said fractional count detector means with the first signals from said input circuit means, and for modifying the phase of the first signal prior to the start of the time base signal, thereby forming phase modified signals, and feedback control means for accepting information from said fractional count detector means and applying information to said fractional count modifier means.

Claim 3

A digital counter as in claim 1 wherein said fractional count modifier means and fractional count detector means include first and second binary circuits connected between said input circuit means and the input of the said digital counting means, and said feedback control means is coupled between the output of said second binary circuit and said first binary circuit to control the state of said first binary circuit as a function of the state of the second binary circuit.

Claim 4

A digital counter as in claim 1 wherein said fractional count modifier means and fractional count detector means include first and second binary circuits connected between said input circuit means and the input of the said digital counting means, and said feedback control means is coupled between the output of said second binary circuit and said first binary circuit to control the state of said first binary circuit as a function of the state of the second binary circuit at the end of the time base signal provided by said time base and control means.

Claim 5

A digital counter as in claim 2 including an additional binary circuit interposed between said input circuit means and said first binary circuit.

Claim 6

A digital counter as in claim 4 wherein said time base and control means resets said additional binary circuit upon reset of said second binary circuit and said digital counting means.

Claim 7

A digital counter as in claim 1 wherein said fractional count modifier means and said fractional count detector means comprise first and second binary circuits connected between said input circuit means and the input of said digital counting means, and said feedback control means comprises gate means coupled to receive signals from said second binary circuit and to apply control signals to said first binary circuit to (a) cause said first binary circuit to assume a first state if said binary circuit is in a second state at the end of the time base signal provided by said time base and control means, and (b) cause said first binary circuit to assume a second state if said second binary circuit is in a first state at the end of said time base signal.

Claim 8

A digital counter as in claim 1 wherein said fractional count modifier means and said fractional count detector means comprise first and second binary circuits coupled with said digital counting means, and said time base and control means provides first and second reset pulses with a first reset pulse being applied to reset said first binary circuit according to the state of said second binary circuit, and a second reset pulse being applied to reset said second binary circuit and said digital counting means.

Claim 9

A digital counter as in claim 6 wherein said time base and control means provides first and second reset pulses with the first reset pulse being applied to reset said first binary circuit according to the state of said second binary circuit, and a second reset pulse being applied to reset said second binary circuit and said digital counting means.

Claim 10

A digital counter as in claim 1 including first binary circuit means forming a predivider for providing a hysteresis effect, said fractional count modifier means and said fractional count detector means including second and third binary circuits connected between said first binary circuit means and the input of said digital counting means, said input circuit means being coupled to said first binary circuit means, and means coupled with said third binary circuit for sampling the state thereof at a predetermined portion of a time base signal provided by said time base and control means and for causing said second binary circuit to assume a state as a function of said state of said third binary circuit.

Claim 11

A digital counter as in claim 1 wherein said time base and control means includes a time base counter having binary means for forming said fractional count modifier means.

Claim 12

A digital counter characterized by stability in the visual readout thereof in the presence of slight freQuency variations in input signals applied to said counter, comprising digital counting means for counting phase modified signals representative of input signals applied thereto over a time base period and providing a visual readout thereof, time base and control means for providing a time base signal independent of the input signals and controlling the application of said phase modified signals to said digital counting means, three binary circuit means preceding the input of said digital counting means for receiving input signals to be counted and for applying phase modified signals to said digital counting means, said first binary circuit means detecting the value of a fractional count occuring during a time base period, said second binary circuit means combining the fractional count of said first binary circuit means with the input signals, thereby modifying the phase of the input signals prior to the start of the time base period, and gate means responsive to the state of the third of said binary circuit means at a predetermined portion of said time base signal and connected to the second of said binary circuit means for allowing said second binary circuit means to assume a state which is a function of said state of said third binary circuit means.

Claim 13

A digital counter characterized by stability in the visual readout thereof in the presence of slight freQuency variations in input signals applied to said counter, comprising digital counting means for counting phase modified signals representative of input signals applied thereto over a time base period and providing a visual readout thereof, time base and control means for providing a time base signal independent of the input signals and controlling the application of said phase modified signals to said digital counting means, three binary circuit means preceding the input of said digital counting means for receiving input signals to be counted and for applying phase modified signals to said digital counting means, said first binary circuit means detecting the value of a fractional count occuring during a time base period, said second binary circuit means combining the fractional count of said first binary circuit means with the input signals, thereby modifying the phase of the input signals prior to the start of the time base period, and gate means responsive to the state of the third of said binary circuit means at a predetermined portion of said time base signal and connected to the second of said binary circuit means for allowing said second binary circuit means to assume a state which is a function of said state of said third binary circuit means.

Claim 14

A counter as in claim 11 wherein said time base and control means resets said first binary circuit means upon reset of said third binary circuit means and said digital counting means after said second binary circuit means has assumed said state.

Claim 17

A method as in claim 13 including the step of additional predividing input signals to be counted before application thereof to said first binary circuit.

Claim 20

A digital counter characterized by reduced jitter in the output thereof comprising input circuit means for receiving input signals to be counted, and for producing first signals representative of the input signals, dIgital counting means for counting phase modified signals applied thereto over a given time base period and providing a readout thereof, time base and control means for providing a time base signal, independent of the input signals and for applying the phase modified signals to said digital counting means, said time base and control means including fractional count modifier means for modifying the phase of the first signals prior to the state of the time base signal, fractional count detector means coupled with said digital counting means for detecting the value of a fractional count occurring during the time base period of said time base and control means, said fractional count modifier means modifying the phase of the first signal in response to the value of the fractional count of said fractional count detector means, and feedback control means for accepting information from said fractional count detector means and applying information to said fractional count modifier means.

Claim 21

A digital counter characterized by reduced jitter in the output thereof comprising input circuit means for receiving input signals to be counted, and for producing first signals representative of the input signals, dIgital counting means for counting phase modified signals applied thereto over a given time base period and providing a readout thereof, time base and control means for providing a time base signal, independent of the input signals and for applying the phase modified signals to said digital counting means, said time base and control means including fractional count modifier means for modifying the phase of the first signals prior to the state of the time base signal, fractional count detector means coupled with said digital counting means for detecting the value of a fractional count occurring during the time base period of said time base and control means, said fractional count modifier means modifying the phase of the first signal in response to the value of the fractional count of said fractional count detector means, and feedback control means for accepting information from said fractional count detector means and applying information to said fractional count modifier means.