Dial pulse and multiple frequency signalling sender/multiple frequency signalling receiver apparatus

Claim 2

In a telephone electronic switching office having a central processing unit (CPU) and a switching network, a dial pulse and multiple frequency signalling sender/multiple frequency signalling receiver apparatus for sending multiple frequency (MF) signals and dial pulse (DP) signals and for receiving MF signals, the apparatus comprising: first means for receiving signals from the CPU and for providing a corresponding parallel binary word, the word comprising bits, said word having a digit portion and a mode portion, second means for generating dial pulse (DP) timing signals when the bits in the mode portion are in a first predetermined order, said DP timing signals corresponding to the digit portion, third means for generating first MF signals when the bits in the mode portion are in the first predetermined order, said first MF signals corresponding to each pulse of the DP timing signals and for generating second MF signals when the bits in the mode portion are in a second predetermined order, said second MF signals corresponding to the digit portion, fourth means for sending DP signals corresponding to the DP timing signals to the switching network and the first MF signals generated by the third means to the CPU, and for sending the second MF signals generated by the third means to the switching network and to the CPU, and in the absence of signals generated by the second and/or third means for receiving MF signals from the switching network and directing the received MF signals to the CPU.

Claim 3

A dial pulse and multiple frequency signalling sender/multiple frequency signalling receiver apparatus for sending multiple frequency (MF) signals and dial pulse (DP) signals and for receiving MF signals in a telephone switching office having at least one central processing unit (CPU) and a switching network, the apparatus comprising: first means for receiving information signals from the CPU on an information bus and providing a corresponding parallel binary word, the word comprising bits, said word having a select portion, a digit portion and a mode portion, enable means for generating an enable pulse in response to at least one ONE bit, in the word, in coincident combination with a CPU enable signal from the CPU, the generated enable pulse being in coincidence with and of a shorter duration of time than the duration of time over which the word is present, parity means for gating the enable pulse in response to a predetermined plurality of sums of the bits in the word, select means for directing the gated enable pulse to one of a plurality of select leads as dictated by the arrangement of the bits in the select portion, a plurality of signal generating means, each separately connected to a select lead of the plurality of select leads, each signal generating means for generating DP timing signals corresponding to the digit portion and first MF signals corresponding to each pulse of the DP timing signals in response to the presence of a directed enable pulse from the select means when the bits in the mode portion are in a first predetermined order, and for generating second MF signals corresponding to the digit portion in response to the presence of a directed enable pulse from the select means when the bits in the mode portion are in a second predetermined order, a plurality of control means, each control means separately connected between one of the plurality of signal generating means and the switching network, each control means for responding to the presence of DP timing signals and first MF signals from the signal generating means by generating DP signals corresponding to the DP timing signals and directing said DP signals to the switching network and directing the first MF signals to the CPU, for responding to the presence of second MF signals from the signal generating means by directing said second MF signals to the switching network and to the CPU, and in the absence of DP timing signals and/or MF signals from the signal generating means for accepting MF signals from the switching network and directing said accepted MF signals to the CPU, a plurality of receiver means each connected between one of the plurality of control means and the CPU, each receiver means for receiving MF signals from the control means and interfacing said received MF signals to the CPU.

Claim 4

A dial pulse and multiple frequency signalling sender/multiple frequency signalling receiver apparatus for sending multiple frequency (MF) signals and dial pulse (DP) signals and for receiving MF signals in a telephone switching office having at least one central processing unit (CPU) and a switching network, the apparatus comprising: first means for receiving information signals from the CPU on an information bus and providing a corresponding parallel binary word, the word comprising bits, said word having a select portion, a digit portion and a mode portion, enable means for generating an enable pulse in response to at least one ONE bit, in the word, in coincident combination with a CPU enable signal from the CPU, the generated enable pulse being in coincidence with and of a shorter duration of time than the duration of time over which the word is present, parity means for gating the enable pulse in response to a predetermined plurality of sums of the bits in the word, select means for directing the gated enable pulse to one of a plurality of select leads as dictated by the arrangement of the bits in the select portion, a plurality of signal generating means, each separately connected to a select lead of the plurality of select leads, each signal generating means for generating DP timing signals corresponding to the digit portion and first MF signals corresponding to each pulse of the DP timing signals in response to the presence of a directed enable pulse from the select means when the bits in the mode portion are in a first predetermined order, and for generating second MF signals corresponding to the digit portion in response to the presence of a directed enable pulse from the select means when the bits in the mode portion are in a second predetermined order, a plurality of control means, each control means separately connected between one of the plurality of signal generating means and the switching network, each control means for responding to the presence of DP timing signals and first MF signals from the signal generating means by generating DP signals corresponding to the DP timing signals and directing said DP signals to the switching network and directing the first MF signals to the CPU, for responding to the presence of second MF signals from the signal generating means by directing said second MF signals to the switching network and to the CPU, and in the absence of DP timing signals and/or MF signals from the signal generating means for accepting MF signals from the switching network and directing said accepted MF signals to the CPU, a plurality of receiver means each connected between one of the plurality of control means and the CPU, each receiver means for receiving MF signals from the control means and interfacing said received MF signals to the CPU.

Claim 5

An apparatus as defined in claim 1 in which each of the plurality of signal generating means comprises: a digit register counter for receiving and storing the digit portion and for altering the digit portion so stored incrementally by one in response to the presence of a count signal, a mode register for receiving and storing the mode portion, the mode register being resetable in response to the presence of a reset signal, a decoder for decoding the digit portion in the digit register, thereby selecting one of a plurality of decoder output leads, one of the plurality of the decoder output leads being connected to the mode register so that when the decoder output lead connected to the mode register is selected the reset signal is supplied to the mode register, an encoder for selecting at least two encoder output leads from a plurality of encoder output leads in response to the selection of a decoder output lead other than the decoder output lead connected to the mode register, a plurality of frequency signal generators, each having an input separately connected to an encoder output lead, each for generating a predetermined frequency in response to the selection of the encoder output lead to which the input of that frequency signal generator is connected, the outputs of the frequency signal generators being connected in common to the control means, means for generating DP timing signals when the bits in the mode portion in the mode register are of the first predetermined order, the output of the means for generating the DP timing signals being connected to the control means and to the digit register counter, whereby each DP timing signal also serves as the count signal, delay means for generating a delayed gating signal after the bits in the mode portion stored in the mode register have been in the first predetermined order for a predetermined period of time, inhibit means for inhibiting the signal generating means from responding to a further directed enable pulse signal from the select means during the generation of DP timing signals, in response to the delayed gating signal.

Claim 6

An apparatus as defined in claim 2 in which said word in addition has a parity portion.

Claim 7

An apparatus as defined in claim 4 in which the select portion consists of four bits, the digit portion consists of four bits, the mode portion consists of two bits and the parity portion consists of at least one bit.

Claim 8

An apparatus as defined in claim 5 in which the plurality of decoder output leads consists of 16 leads and the plurality of encoder output leads consists of six leads.

Claim 9

An apparatus as defined in claim 3 in which said word in addition has a parity portion.

Claim 10

An apparatus as defined in claim 7 in which the select portion consists of four bits, the digit portion consists of four bits, the mode portion consists of two bits and the parity portion consists of at least one bit.

Claim 11

An apparatus as defined in claim 8 in which the plurality of decoder output leads consists of 16 leads and the plurality of encoder output leads consists of six leads.