Monolithic analog-to-digital converter

Claim 2

A converter for converting an analog voltage signal to a quantized signal, comprising: voltage generating means for developing a linearly varying ramp voltage having predetermined time-voltage characteristics, said voltage generating means having a constant current source and a capacitor connected in series, said current source including, a first FET having a first drain coupled to one side of said capacitor, a first source for connection to a source of potential, and a first gate, said first gate being biased to a temperature critical potential chosen by determining the intersection of different temperature transfer characteristics of said first FET, whereby the current flow through said first FET is maintained constant and independent of temperature changes over a predetermined range of temperatures; voltage comparing means responsive to an unknown input voltage and said ramp voltage, and operative to compare said voltages and develop a coincident signal when they are equal; and means responsive to said coincident signal for developing an output signal commensurate with said unknown voltage.

Claim 3

A converter as recited in claim 1 wherein said voltage comparing means includes a first differential amplifier, and said means responsive to said coincidence signal includes, a flip-flop for developing said output signal, a second differential amplifier for driving said flip-flop, and a cross-over network for coupling the output terminals of said first differential amplifier into the input terminals of said second differential amplifier.

Claim 4

A converter as recited in claim 1 wherein said voltage generating means further includes, a first switching means in series with said first FET and said capacitor, and a second switching means in parallel with said capacitor.

Claim 5

A converter as recited in claim 3 wherein said first switching means includes a second FET, and said second switching means includes a third FET, said second and third FETs being biased to have opposite conductivity states.

Claim 6

A converter for converting an analog voltage signal to a quantized signal, comprising: voltage generating means for developing a linearly varying ramp voltage having predetermined time-voltage characteristics, said voltage generating means including, a constant current source, a capacitor and a first switching means connected in series, and a second switching means connected in parallel with said capacitor, said capacitor having a first electrode for connection to a first source of potential, and a second electrode, said current source including a first FET having a first drain coupled to said second electrode, a first source for connection to a second source of potential, and a first gate for receiving a temperature critical voltage, said first FET being responsive to said temperature critical voltage and operative to provide a fixed current for charging said capacitor at a linear rate independent of temperature, said second switching means including a second FET having a second drain coupled to said first electrode, a second source coupled to said second electrode, and a second gate for receiving a shorting signal, said second FET being resPonsive to said shorting signal and operative to discharge said capacitor; voltage comparing means responsive to an unknown input voltage and said ramp voltage, and operative to compare said voltages and develop a coincidence signal when they are equal; and means responsive to said coincidence signal for developing an output signal commensurate with said unknown voltage.

Claim 7

A converter for converting an analog voltage signal to a quantized signal, comprising: voltage generating means for developing a linearly varying ramp voltage having predetermined time-voltage characteristics, said voltage generating means including, a constant current source, a capacitor and a first switching means connected in series, and a second switching means connected in parallel with said capacitor, said capacitor having a first electrode for connection to a first source of potential, and a second electrode, said current source including a first FET having a first drain coupled to said second electrode, a first source for connection to a second source of potential, and a first gate for receiving a temperature critical voltage, said first FET being responsive to said temperature critical voltage and operative to provide a fixed current for charging said capacitor at a linear rate independent of temperature, said second switching means including a second FET having a second drain coupled to said first electrode, a second source coupled to said second electrode, and a second gate for receiving a shorting signal, said second FET being resPonsive to said shorting signal and operative to discharge said capacitor; voltage comparing means responsive to an unknown input voltage and said ramp voltage, and operative to compare said voltages and develop a coincidence signal when they are equal; and means responsive to said coincidence signal for developing an output signal commensurate with said unknown voltage.

Claim 8

An analog-to-digital converter as recited in claim 5 wherein said voltage generating means further includes a third FET having a third drain coupled to said first source, a third source for connection to said second source of potential, and a third gate responsive to a switching signal, said third FET being responsive to said switching signal and operative to interrupt current flow from said second source of potential to said capacitor.

Claim 9

In a monolithic analog-to-digital converter including, a voltage generating means for developing a ramp voltage which changes linearly with time, a comparator responsive to an unknown voltage and said ramp voltage and operative to develop a coincidence signal when said ramp voltage equals said unknown voltage, and signal generating means responsive to said coincidence signal and operative to develop an output signal commensurate with the magnitude of said unknown voltage, an improved voltage generating means, comprising: a capacitor having a first capacitive plate for connection to a first potential supply and a second capacitive plate; a first FET having a first drain coupled to said second capacitive plate, a first source for connection to a second potential supply, and a first gate for receiving a temperature critical voltage, said first FET being responsive to said temperature critical voltage and operative to provide a fixed charging current to said capacitor which is independent of temperature; and a second FET having a second drain coupled to said first capacitive plate, a second source coupled to said second capacitive plate, and a second gate for receiving a shorting signal, said second FET being responsive to said shorting signal and operative to discharge said capacitor.

Claim 10

In a monolithic analog-to-digital converter including, a voltage generating means for developing a ramp voltage which changes linearly with time, a comparator responsive to an unknown voltage and said ramp voltage and operative to develop a coincidence signal when said ramp voltage equals said unknown voltage, and signal generating means responsive to said coincidence signal and operative to develop an output signal commensurate with the magnitude of said unknown voltage, an improved voltage generating means, comprising: a capacitor having a first capacitive plate for connection to a first potential supply and a second capacitive plate; a first FET having a first drain coupled to said second capacitive plate, a first source for connection to a second potential supply, and a first gate for receiving a temperature critical voltage, said first FET being responsive to said temperature critical voltage and operative to provide a fixed charging current to said capacitor which is independent of temperature; and a second FET having a second drain coupled to said first capacitive plate, a second source coupled to said second capacitive plate, and a second gate for receiving a shorting signal, said second FET being responsive to said shorting signal and operative to discharge said capacitor.

Claim 11

In a monolithic analog-to-digital converter as recited in claim 7 wherein said temperature critical voltage is determined by the intersection of the different temperature transfer characteristic curves of said first FET.