Balanced semiconductor switching network circuit and construction

Claim 2

A coordinate switching network comprising a plurality of first conductors arranged in one set of coordinates, a plurality of second conductors arranged in a second set of coordinates and intersecting said first conductors to define a coordinate array of crosspoints, a plurality of semiconductor eleMents connecting each of said first conductors with each of said second conductors at alternate ones of said crosspoints in each of said sets of coordinates, each of said semiconductor elements presenting a particular capacitance to alternating current at a predetermined frequency when in the inactive state, and a plurality of capacitor means connecting each of said first conductors with each of said second conductors at the other alternate ones of said crosspoints in each of said sets of coordinates, each of said capacitor means presenting said particular capacitance.

Claim 3

A coordinate switching network comprising a plurality of groups of first conductors arranged in one set of coordinates, a plurality of groups of second conductors arranged in a second set of coordinates and intersecting said first conductors to define a coordinate array of groups of crosspoints, a plurality of semiconductor elements connecting each of said first conductors with each of said second conductors at the crosspoints of alternate groups of said groups of crosspoints in each of said sets of coordinates, each of said semiconductor elements presenting a particular capacitance to alternating current at a predetermined frequency when in the inactive state, and a plurality of capacitor means connecting each of said first conductors with each of said second conductors at the crosspoints of the other alternate groups of said groups of crosspoints, each of said capacitor means presenting said particular capacitance.

Claim 4

A coordinate switching network comprising a plurality of groups of first conductors arranged in one set of coordinates, a plurality of groups of second conductors arranged in a second set of coordinates and intersecting said first conductors to define a coordinate array of groups of crosspoints, a plurality of semiconductor elements connecting each of said first conductors with each of said second conductors at the crosspoints of alternate groups of said groups of crosspoints in each of said sets of coordinates, each of said semiconductor elements presenting a particular capacitance to alternating current at a predetermined frequency when in the inactive state, and a plurality of capacitor means connecting each of said first conductors with each of said second conductors at the crosspoints of the other alternate groups of said groups of crosspoints, each of said capacitor means presenting said particular capacitance.

Claim 5

A coordinate switching network according to claim 2 in which said groups of first conductors and said groups of second conductors each comprise tip and ring conductors of balanced transmission paths through said network.

Claim 6

A coordinate switching network according to claim 3 in which each of said semiconductor elements comprises a PNPN thyristor having its anode connected to a first conductor and its cathode connected to a second conductor.

Claim 7

A coordinate switching network comprising a plurality of pairs of first conductors arranged in one set of coordinates, a plurality of pairs of second conductors arranged in a second set of coordinates and intersecting said pairs of first conductors to define a coordinate array of groups of crosspoints, a plurality of semiconductor elements connecting each conductor of said pairs of first conductors with the corresponding conductor of each of said pairs of second conductors at the crosspoints of alternate groups of said groups of crosspoints in each set of coordinates, each of said semiconductor elements presenting a particular capacitance to alternating current at a predetermined frequency when in the inactive state, and a plurality of capacitor means connecting each conductor of said pairs of first conductors with the corresponding conductor of each of said pairs of second conductors at the crosspoints of the other alternate groups of said groups of crosspoints, each of said capacitor means presenting said particular capacitance.

Claim 8

A coordinate switching network comprising a plurality of pairs of first conductors arranged in one set of coordinates, a plurality of pairs of second conductors arranged in a second set of coordinates and intersecting said pairs of first conductors to define a coordinate array of groups of crosspoints, a plurality of semiconductor elements connecting each conductor of said pairs of first conductors with the corresponding conductor of each of said pairs of second conductors at the crosspoints of alternate groups of said groups of crosspoints in each set of coordinates, each of said semiconductor elements presenting a particular capacitance to alternating current at a predetermined frequency when in the inactive state, and a plurality of capacitor means connecting each conductor of said pairs of first conductors with the corresponding conductor of each of said pairs of second conductors at the crosspoints of the other alternate groups of said groups of crosspoints, each of said capacitor means presenting said particular capacitance.

Claim 9

A coordinate switching network according to claim 5 also comprising a transformer winding connected between one end of each of said pairs of said first conductors and one end of each of said pairs of said second conductors, each of said transformer windings having a grounded center-tap.

Claim 10

A coordinate switching network construction comprising a planar mounting plate, a plurality of first conductors arranged in one set of coordinates on one side of said plate, a plurality of second conductors arranged in a second set of coordinates on the other side of said plate and intersecting said first conductors to define a coordinate array of crosspoints, said plate having a plurality of apertures therein at alternate ones of said crosspoints in each of said sets of coordinates, a plurality of semiconductor elements connecting each of said first conductors with each of said second conductors through said apertures, and a plurality of capacitor means connecting each of said first conductors with each of said second conduCtors at the other alternate ones of said crosspoints in each of said sets of coordinates, said capacitor means at each of said last-mentioned crosspoints comprising the intersection of said first and second conductors having therebetween a dielectric comprising a section of said plate defined by said intersection.

Claim 11

A coordinate switching network construction comprising a planar mounting plate, a plurality of first conductors arranged in one set of coordinates on one side of said plate, a plurality of second conductors arranged in a second set of coordinates on the other side of said plate and intersecting said first conductors to define a coordinate array of crosspoints, said plate having a plurality of apertures therein at alternate ones of said crosspoints in each of said sets of coordinates, a plurality of semiconductor elements connecting each of said first conductors with each of said second conductors through said apertures, and a plurality of capacitor means connecting each of said first conductors with each of said second conduCtors at the other alternate ones of said crosspoints in each of said sets of coordinates, said capacitor means at each of said last-mentioned crosspoints comprising the intersection of said first and second conductors having therebetween a dielectric comprising a section of said plate defined by said intersection.

Claim 12

A coordinate switching network construction comprising a planar mounting plate, a plurality of groups of first conductors arranged in one set of coordinates on one side of said plate, a plurality of groups of second conductors arranged in a second set of coordinates on the other side of said plate and intersecting said groups of first conductors to define a coordinate array of groups of crosspoints, said plate having a plurality of apertures therein at alternate ones of said groups of crosspoints in each of said sets of coordinates, a plurality of semiconductor elements connecting each of said first conductors with each of said second conductors through said apertures, and a plurality of capacitor means connecting each of said first conductors with each of said second conductors at the other alternate ones of said groups of crosspoints in each of said sets of coordinates, said capacitor means at each of said last-mentioned crosspoints comprising the intersection of said first and second conductors having therebetween a dielectric comprising a section of said plate defined by said intersection.

Claim 13

A coordinate switching network construction comprising a planar mounting plate, a plurality of groups of first conductors arranged in one set of coordinates on one side of said plate, a plurality of groups of second conductors arranged in a second set of coordinates on the other side of said plate and intersecting said groups of first conductors to define a coordinate array of groups of crosspoints, said plate having a plurality of apertures therein at alternate ones of said groups of crosspoints in each of said sets of coordinates, a plurality of semiconductor elements connecting each of said first conductors with each of said second conductors through said apertures, and a plurality of capacitor means connecting each of said first conductors with each of said second conductors at the other alternate ones of said groups of crosspoints in each of said sets of coordinates, said capacitor means at each of said last-mentioned crosspoints comprising the intersection of said first and second conductors having therebetween a dielectric comprising a section of said plate defined by said intersection.

Claim 14

A coordinate switching network construction as claimed in claim 8 in which each of said semiconductor elements presents a particular capacitance to an alternating current of a predetermined frequency when in an inactive state and in which said first and second conductors and the cross section of said plate are so dimensioned that each of said capacitor means presents said particular capacitance.

Claim 15

A coordinate switching network arrangement comprising a plurality of groups of first conductors arranged in one set of coordinates of said network, a plurality of groups of second conductors arranged in a second set of coordinates and intersecting said groups of first conductors to define a coordinate array of crosspoints, a plurality of semiconductor elements connecting each of said first conductors with each of said second conductors at alternate ones of said groups of crosspoints in each of said sets of coordinates, and a plurality of capacitor means connecting each of said first conductors with each of said second conductors at the other alternate ones of said groups of crosspoints in each of said sets of coordinates, said capacitor means at each of said last-mentioned crosspoints comprising portions of each of said first and second conductors defined by the intersecting other of said last-mentioned first and second conductors and a dielectric material interposed between said portions.

Claim 16

A coordinate switching network arrangement comprising a plurality of groups of first conductors arranged in one set of coordinates of said network, a plurality of groups of second conductors arranged in a second set of coordinates and intersecting said groups of first conductors to define a coordinate array of crosspoints, a plurality of semiconductor elements connecting each of said first conductors with each of said second conductors at alternate ones of said groups of crosspoints in each of said sets of coordinates, and a plurality of capacitor means connecting each of said first conductors with each of said second conductors at the other alternate ones of said groups of crosspoints in each of said sets of coordinates, said capacitor means at each of said last-mentioned crosspoints comprising portions of each of said first and second conductors defined by the intersecting other of said last-mentioned first and second conductors and a dielectric material interposed between said portions.

Claim 17

A coordinate switching network arrangement as claimed in claim 10 in which said dielectric material comprises a portion of a planar plate having mounted thereon on opposite sides, respectively, said plurality of groups of first conductors and said plurality of groups of second conductors.

Claim 18

A coordinate switching network arrangement as claimed in claim 11 in which said plate has apertures provided therein at said alternate ones of said groups of crosspoints and said plurality of semiconductor elements comprise thyristors mounted on a single chip within each of said apertures.

Claim 19

A coordinate switching network arrangement as claimed in claim 12 in which said dielectric material is glass.