Burst error detection and correction system

Claim 2

A data communication system comprising: a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data signal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, and means responsive to said indicating means indicating a burst error and said record means recoding only one burst error for correcting the burst error in said data segment at the address indicated in said burst error address register with the parity word generated by said parity word generator.

Claim 3

The data communication system claimed in claim 1 having means to determine the number of bits in a burst error to be corrected.

Claim 4

A data communication system comprising: a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data signal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, means responsive to said indicating means indicating a burst error and said recording means recoding only one burst error for shifting said data segment out of said shift register one bit at a time, said shift counter responsive to shift of data bits out of said shift register for counting said bits of data, means for comparing the count of bits shifted out of said shift counter with the contents of said burst error address register and indicating a match between them, and means responsive to the indication of a match by said comparison means for exclusive oring said data bits and saId corresponding parity word to complement said burst errors.

Claim 5

A data communication system comprising: a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data signal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, means responsive to said indicating means indicating a burst error and said recording means recoding only one burst error for shifting said data segment out of said shift register one bit at a time, said shift counter responsive to shift of data bits out of said shift register for counting said bits of data, means for comparing the count of bits shifted out of said shift counter with the contents of said burst error address register and indicating a match between them, and means responsive to the indication of a match by said comparison means for exclusive oring said data bits and saId corresponding parity word to complement said burst errors.

Claim 6

The data communication system claimed in claim 3 including a burst length counter set to a predetermined count by the indication of a burst error, means responsive to the shift of bits out of said shift register after the indication of a burst error for decrementing said burst length counter, and means responsive to said burst length counter when it has been decremented to zero for inhibiting the exclusive oring of said data bits and said corresponding parity word.