US3725689A
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Cellular correlation array
Assignee: United States Department of the Navy
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Filing: 1971-08-03
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Granted: 1973-04-03
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Expires: 1991-08-03
Abstract
Abstract The cellular array is capable of cross-correlating two binary sequences and automatically determining the coordinates of the peak of the cross-correlation function. The array includes two input registers, a binary counting array, and several peripheral registers.
Inventors
- 👤 W Kautz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:48
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/15; H; H04; H04L; H04L23/00; H04L23/02
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
156 words
A cellular correlation array for determining the crosscorrelation between two binary sequences comprising: means for storing a first binary sequence, said sequence being of a particular length n; shift register means for shifting a second, repetitious binary sequence, having a period N times said first binary sequence coupled to said storing means; comparing means coupled to said storing means and said shift register means for comparing said first binary sequence with a corresponding length of said second sequence to provide outputs which are a function of a correlation; counting array means coupled to said comparing means for totaling the outputs of said comparing means wherein an output of said counting array means represents a correlation function peak; means for determining at which time the correlation function peak ends; output means coupled to said time determining means and to said counting array means for providing the correlation function peak and the time at which the peak occurred.
Claim 2
Dependent Claim
156 words
A cellular correlation array for determining the crosscorrelation between two binary sequences comprising: means for storing a first binary sequence, said sequence being of a particular length n; shift register means for shifting a second, repetitious binary sequence, having a period N times said first binary sequence coupled to said storing means; comparing means coupled to said storing means and said shift register means for comparing said first binary sequence with a corresponding length of said second sequence to provide outputs which are a function of a correlation; counting array means coupled to said comparing means for totaling the outputs of said comparing means wherein an output of said counting array means represents a correlation function peak; means for determining at which time the correlation function peak ends; output means coupled to said time determining means and to said counting array means for providing the correlation function peak and the time at which the peak occurred.
Claim 3
Dependent Claim
24 words
The cellular correlation array of claim 1 wherein said means for determining at which time the correlation function peak ends comprises at storage register.
Claim 4
Dependent Claim
23 words
The cellular correlation array of claim 1 wherein said comparing means comprises exclusive-OR logic to provide a multiplying function in the correlation process.
Claim 5
Dependent Claim
33 words
The cellular correlation array of claim 1 wherein said counting array means comprises an array of columns and rows of interconnected cells each of said cells being capable of performing elementary binary addition.
Claim 6
Dependent Claim
34 words
The cellular correlation array of claim 1 wherein the counting array means comprises a storage register having a plurality of stages in which each stage is coupled to the next stage by majority logic.
Claim 7
Dependent Claim
49 words
The cellular correlation array of claim 1 wherein each of said cells has a first and second input, wherein a first output is produced by means for ANDING said first and second inputs and a second output is the product of exclusive-OR means of said first and second inputs.
Claim 8
Independent Claim
218 words
A device for determining the maximum value of a binary function and its time of occurrence comprising: a first shift register means for storing the value of said binary function, said first shift register means comprising a plurality of cells; each cell including a bistable storage device having a first and second output and a majority logic gate; a second shift register means for storing the time of occurrence of each change of said binary function being coupled to said second output of said plurality of cells; clock means coupled to said first and second shift register for continuously supplying clock pulses; a first input of said bistable storage device being representative of one binary bit of said binary function being connected to said majority logic gate; a second input of said bistable storage device being connected to the output of the majority logic gate of the previous cell; said first output of said bistable device being connected to said majority logic gate; a third input being connected to said bistable storage device and said second shift register for gating said bistable storage device to receive said first input and to advance said second shift register by one clock pulse respectively when the value of said binary function is of a value greater than the previously stored value.
Claim 9
Independent Claim
218 words
A device for determining the maximum value of a binary function and its time of occurrence comprising: a first shift register means for storing the value of said binary function, said first shift register means comprising a plurality of cells; each cell including a bistable storage device having a first and second output and a majority logic gate; a second shift register means for storing the time of occurrence of each change of said binary function being coupled to said second output of said plurality of cells; clock means coupled to said first and second shift register for continuously supplying clock pulses; a first input of said bistable storage device being representative of one binary bit of said binary function being connected to said majority logic gate; a second input of said bistable storage device being connected to the output of the majority logic gate of the previous cell; said first output of said bistable device being connected to said majority logic gate; a third input being connected to said bistable storage device and said second shift register for gating said bistable storage device to receive said first input and to advance said second shift register by one clock pulse respectively when the value of said binary function is of a value greater than the previously stored value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-02 | 1976-10-02 | 1977-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-02 | 1980-10-02 | 1981-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-02 | 1984-10-02 | 1985-04-03 | $7700.00 | Window Closed / Lapsed |