US3725688A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital subtraction device
Assignee: United States Atomic Energy Commission
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Filing: 1971-09-03
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Granted: 1973-04-03
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Expires: 1991-09-03
Abstract
Abstract This circuit acts to subtract a first series of pulses from a second series of pulses. The second series of pulses is coupled directly to an output terminal of the circuit until a first series pulse is counted in one direction by an up-down counter. With a count greater than zero in the up-down counter, the second series of pulses is coupled thereto to count in the opposite direction. With the up-down counter having a count greater than zero, the second series of pulses are also blocked from the output terminal of the subtraction device.
Inventors
- 👤 G Brunson
- 👤 R Curran
- 👤 F Just
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:21
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/605; G01; G01T; G01T1/00; G01T1/16; G01T1/17; G01T1/178; H; H03; H03K; H03K21/00; H03K21/02
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
288 words
A circuit for subtracting a first series of pulses from a second series of pulses comprising, output terminal means, a first input terminal for receiving said first series of pulses and a second input terminal for receiving said second series of pulses, bidirectional counter means responsive to a zero count therein to develop a first control signal and to a count therein different from zero to develop a second control signal, said bidirectional counter means being coupled to said first input terminal to receive said first series of pulses therefrom and to count in a first direction in response thereto, a first AND gate having a first input coupled to said bidirectional counter means for receiving said first and second control signals and a second input coupled to said second input terminal for receiving said second series of pulses, said first AND gate further having an output coupled to said bidirectional counter means, a second AND gate having one input coupled to said bidirectional counter means for receiving said first and second control signals and a second input coupled to said second input terminal for receiving said second series of pulses, said second AND gate further having an output coupled to said output terminal, said first control signal acting to disable said first AND gate and enable said second AND gate so that said second series of pulses is directed to said output terminal, said second control signal acting to enable said first AND gate and disable said second AND gate so that said second series of pulses is directed to said bidirectional counter means, said bidirectional counter means being responsive to said second series of pulses to count in a second direction opposite to said first direction.
Claim 2
Dependent Claim
288 words
A circuit for subtracting a first series of pulses from a second series of pulses comprising, output terminal means, a first input terminal for receiving said first series of pulses and a second input terminal for receiving said second series of pulses, bidirectional counter means responsive to a zero count therein to develop a first control signal and to a count therein different from zero to develop a second control signal, said bidirectional counter means being coupled to said first input terminal to receive said first series of pulses therefrom and to count in a first direction in response thereto, a first AND gate having a first input coupled to said bidirectional counter means for receiving said first and second control signals and a second input coupled to said second input terminal for receiving said second series of pulses, said first AND gate further having an output coupled to said bidirectional counter means, a second AND gate having one input coupled to said bidirectional counter means for receiving said first and second control signals and a second input coupled to said second input terminal for receiving said second series of pulses, said second AND gate further having an output coupled to said output terminal, said first control signal acting to disable said first AND gate and enable said second AND gate so that said second series of pulses is directed to said output terminal, said second control signal acting to enable said first AND gate and disable said second AND gate so that said second series of pulses is directed to said bidirectional counter means, said bidirectional counter means being responsive to said second series of pulses to count in a second direction opposite to said first direction.
Claim 3
Dependent Claim
110 words
The subtracting circuit of claim 1 wherein, said counter means includes a plurality of binary stages with each of said binary stages having a 0 state and a 1 state, said bidirectional counter means further including a third AND gate having inputs coupled to each of said binary states and an output coupled to said first and second AND gates, said third AND gate being responsive to said states of said binary stages to develop said first control signal with all of said binary stages being in a 0 state and to develop said second control signal with at least one of said binary stages being in a 1 state.
Claim 4
Dependent Claim
28 words
The subtracting circuit of claim 2 further including, output counter means coupled to said output terminal to count said second series of pulses coupled to said output terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-02 | 1976-10-02 | 1977-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-02 | 1980-10-02 | 1981-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-02 | 1984-10-02 | 1985-04-03 | $7700.00 | Window Closed / Lapsed |