US3725686A
Expired / Lapsed
US
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Polyphasor generation by vector addition and scalar multiplication
Assignee: Raytheon Co
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Filing: 1971-01-29
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Granted: 1973-04-03
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Expires: 1991-01-29
Abstract
Abstract Herein is disclosed the method and apparatus for producing angular rotations of an input signal (phasor). The method involves phase shifting the input signal by a preselected amount, vectorially adding the input and the phase shifted signals, and then adjusting the amplitude of the sum phasor by a scalar multiplication operation. The addition and multiplication steps are repeated in a plurality of subsequent processing operations whereby various combinations of phasor signals produced during preceding steps are summed and amplitude adjusted to obtain a set of output signals having preselected phase values.
Inventors
- 👤 G Ustach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:04
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/548; G06F17/00; G06F17/10; G06F17/16; H; H03; H03H; H03H17/00; H03H17/08
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
102 words
A device for providing phase rotated output signals in response to a pair of input signals of equal magnitudes and differing phase angles applied thereto, said device comprising; a plurality of cascaded processor stages with each stage including means for forming the sum of at least one pair of signals from a group of signals consisting of said input signals and output signals of preceding processor stages, and each stage further including means coupled to said sum forming means for adjusting the magnitude of the sum signals formed therein to provide output signals approximately equal to the magnitude of said input signals.
Claim 2
Independent Claim
102 words
A device for providing phase rotated output signals in response to a pair of input signals of equal magnitudes and differing phase angles applied thereto, said device comprising; a plurality of cascaded processor stages with each stage including means for forming the sum of at least one pair of signals from a group of signals consisting of said input signals and output signals of preceding processor stages, and each stage further including means coupled to said sum forming means for adjusting the magnitude of the sum signals formed therein to provide output signals approximately equal to the magnitude of said input signals.
Claim 3
Dependent Claim
78 words
The device of claim 1 wherein said sum forming mEans of each processor stage subsequent to the first stage includes a plurality of adders and means for applying a different pair of signals from said group of signals to each of said adders, with each said pair of signals applied to adders of a particular stage having a phase angle difference therebetween equal to the incremental phase difference between the output signals of the last preceding processor stage.
Claim 4
Dependent Claim
31 words
The device of claim 1 wherein said sum forming means includes at least one adder in each stage and said magnitude adjusting means includes a multiplication unit associated with each adder.
Claim 5
Dependent Claim
43 words
The device of claim 3 wherein the multiplier constant of said multiplier units is approximately equal to 1/(2 cos theta /2n) where theta is the phase angle between said pair of input signals and n is the order of the associated processor stage.
Claim 6
Dependent Claim
65 words
The device of claim 1 wherein said plurality of processor stages include: a first processor stage coupled to receive said pair of input signals; and a plurality of series coupled subsequent processor stages with each stage coupled to receive pairs of signals from a group of signals consisting of said input signals, said first stage output signal, and the output signals of preceding processors stages.
Claim 7
Dependent Claim
73 words
The device of claim 1 wherein said sum forming means of each processor stage includes an adder and each processor stage, subsequent to the first stage, includes a switch coupled between the preceding stage and the adder of the associated stage; whereby the signal applied to one input of the associated adder is selectable and the phase angle of the output signal of said device is controlled by the settings of said switches.
Claim 8
Dependent Claim
25 words
The device of claim 6 wherein the other input of said associated adders is coupled to the magnitude adjusting means of the preceding processor stage.
Claim 9
Dependent Claim
18 words
The device of claim 6 wherein said magnitude adjusting means includes a multiplication unit associated with each adder.
Claim 10
Dependent Claim
43 words
The device of claim 8 wherein the multiplier constant of said multiplier units is approximately equal to 1/(2 cos theta /2n) where theta is the phase angle between said pair of input signals and n is the order of the associated processor stage.
Claim 11
Independent Claim
157 words
A device for forming a plurality of phase rotated output signals in response to an applied input signal, said device comprising: means for phase shifting the applied signal by approximately 120*; means for adding said applied signal and said 120* phase shifted signal to provide a first output signal; means for phase shifting the applied signal and said 120* phase shifted signal by plus and minus 90*, respectively, to provide second and third output signals; and a plurality of cascaded processor stages with each stage comprising means for forming the sum of various pairs of signals from a group of signals consisting of said input signal, said first, second and third output signals and the output signals of preceding processors stages; and each stage further including means coupled to said sum forming means for adjusting the magnitude of the sum signals formed therein to produce an output signal equal to the magnitude of said applied input signal.
Claim 12
Independent Claim
157 words
A device for forming a plurality of phase rotated output signals in response to an applied input signal, said device comprising: means for phase shifting the applied signal by approximately 120*; means for adding said applied signal and said 120* phase shifted signal to provide a first output signal; means for phase shifting the applied signal and said 120* phase shifted signal by plus and minus 90*, respectively, to provide second and third output signals; and a plurality of cascaded processor stages with each stage comprising means for forming the sum of various pairs of signals from a group of signals consisting of said input signal, said first, second and third output signals and the output signals of preceding processors stages; and each stage further including means coupled to said sum forming means for adjusting the magnitude of the sum signals formed therein to produce an output signal equal to the magnitude of said applied input signal.
Claim 13
Dependent Claim
38 words
The device of claim 10 wherein said sum forming means of each processor stage includes a plurality of adders and means for applying a different pair of signals from said group of signals to each of said adders.
Claim 14
Dependent Claim
31 words
The device of claim 10 wherein said sum forming means includes a plurality of adders in each stage and said magnitude adjusting means includes a multiplication unit associated with each adder.
Claim 15
Dependent Claim
24 words
The device of claim 12 wherein the multiplier constant of the multiplier units is a function of the order of the associated processor stage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-02 | 1976-10-02 | 1977-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-02 | 1980-10-02 | 1981-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-02 | 1984-10-02 | 1985-04-03 | $7700.00 | Window Closed / Lapsed |