Method and circuit arrangement for displaying or recording a sequence of binary bits

Claim 2

In a method for representing a sequence of binary bits by varying an output signal between two states, the lengths of the intervals between successive state changes being indicative of the bit values, the improvement comprising the steps of: comparing the values of each succeeding pair of bits of the sequence; and causing the interval between each corresponding state change and its preceding state change to have one magnitude when the bits compared have the same value and to have a different magnitude when the bits compared have opposite values.

Claim 3

A method as defined in claim 1 wherein the ratio of the two interval magnitudes is 1:2.

Claim 4

A method as defined in claim 1 comprising the further step of replacing two consecutive larger magnitude intervals by an interval whose magnitude is smaller than the total magnitude of the two intervals.

Claim 5

A circuit arrangement for representing a sequence of binary bits by a signal which undergoes a series of changes in state with the interval between successive state changes having one magnitude when a corresponding pair of bits have the same value and a different magnitude when the corresponding pair of bits have opposite values, said circuit comprising: gate means having two inputs and arranged to produce an output having a first value when the signals at its two inputs are identical and a second value when the signals at its two inputs are non-identical; means for delivering, in a timed sequence, successive pairs of the binary bits to said gate means inputs; switching means for producing thE bit sequence-representing and for changing the state thereof in time dependence on the delivery of each pair of bits; blocking means for temporarily inhibiting the creation of a state change; and logic means connected to said blocking means for rendering it effective for a predetermined period of time only when the output from said gate means has one of its values.

Claim 6

A circuit arrangement for representing a sequence of binary bits by a signal which undergoes a series of changes in state with the interval between successive state changes having one magnitude when a corresponding pair of bits have the same value and a different magnitude when the corresponding pair of bits have opposite values, said circuit comprising: gate means having two inputs and arranged to produce an output having a first value when the signals at its two inputs are identical and a second value when the signals at its two inputs are non-identical; means for delivering, in a timed sequence, successive pairs of the binary bits to said gate means inputs; switching means for producing thE bit sequence-representing and for changing the state thereof in time dependence on the delivery of each pair of bits; blocking means for temporarily inhibiting the creation of a state change; and logic means connected to said blocking means for rendering it effective for a predetermined period of time only when the output from said gate means has one of its values.

Claim 7

An arrangement as defined in claim 4 wherein said logic means are composed of two paths one of which transmits a signal only when the output from said gate means has said first value and the other of which transmits a signal only when the output from said gate means has said second value, and further comprising switching means for selectively connecting the input of said blocking means exclusively to either one of said paths.