Data communication system

Claim 3

The system defined in claim 1 wherein n 5.

Claim 4

a count word associated with each input line for timing a character transmission thereover; D. a register; E. means operating in conjunction with such scanner to increment, during each sampling, the count word associated with input lines over which character transmissions are in progress,

Claim 5

a count word associated with each input line for timing a character transmission thereover; D. a register; E. means operating in conjunction with such scanner to increment, during each sampling, the count word associated with input lines over which character transmissions are in progress,

Claim 6

load the character bit being transmitted over the input line into said register, and

Claim 7

load the character bit being transmitted over the input line into said register, and

Claim 8

a decoder operating to selected a particular input line for sampling on the basis of the line number held in said line selection register.

Claim 9

a decoder operating to selected a particular input line for sampling on the basis of the line number held in said line selection register.

Claim 10

means for decrementing said second register each time an assembled character is processed during a sampling cycle, and inhibiting the processing of additional assembled characters during the sampling cycle in progress when said register content is zero, a. said additional assembled characters being processed during subsequent sampling cycles.

Claim 11

means for decrementing said second register each time an assembled character is processed during a sampling cycle, and inhibiting the processing of additional assembled characters during the sampling cycle in progress when said register content is zero, a. said additional assembled characters being processed during subsequent sampling cycles.

Claim 12

a line status word associated with each input line, said line status words including a. a count word portion for timing a character transmission; D. a first register adapted to temporarily hold the line status word of each input line as it is sampled during a sampling cycle; E. means incrementing the count word portion of a line status word each time it is held in said first register during a character transmission over the associated input line; F. assembly means responsive to the count word portion of each line status word each time it cycles to a predetermined count to transfer the correspondingly associated character assembly word into said first register, enter the character bit being transmitted over the associated input line for assembly into said character assembly word; and return said character assembly word to said memory; G. means detecting when all of the bits of a character have been transmitted over an input line and assembled into the associated character assembly word; and H. means controlling the processing of assembled characters, said means including

Claim 13

a line status word associated with each input line, said line status words including a. a count word portion for timing a character transmission; D. a first register adapted to temporarily hold the line status word of each input line as it is sampled during a sampling cycle; E. means incrementing the count word portion of a line status word each time it is held in said first register during a character transmission over the associated input line; F. assembly means responsive to the count word portion of each line status word each time it cycles to a predetermined count to transfer the correspondingly associated character assembly word into said first register, enter the character bit being transmitted over the associated input line for assembly into said character assembly word; and return said character assembly word to said memory; G. means detecting when all of the bits of a character have been transmitted over an input line and assembled into the associated character assembly word; and H. means controlling the processing of assembled characters, said means including

Claim 14

means for decrementing said load distribution register each time an assembled character is processed during a sampling cycle, and inhibiting the processing of additional assembled characters during the sampling cycle in progress when said load distribution register content is zero, a. said additional assembled characters being processed during subsequent sampling cycles.

Claim 15

means for decrementing said load distribution register each time an assembled character is processed during a sampling cycle, and inhibiting the processing of additional assembled characters during the sampling cycle in progress when said load distribution register content is zero, a. said additional assembled characters being processed during subsequent sampling cycles.

Claim 16

return the character assembly word to said memory.

Claim 17

return the character assembly word to said memory.

Claim 20

The system defined in claim 3, wherein n equals 5.

Claim 21

The system defined in claim 3, wherein said memory stores a line status word associated with each input line,

Claim 22

The system defined in claim 5, wherein each said count word is included as a portion of a correspondingly associated one of said line status words.

Claim 23

The system defined in claim 6, wherein each said line status word further includes a status bit, and said system further includes: A. means for coding said status bit to indicate that the associated input line has been found active during a sampling thereof.

Claim 24

The system defined in claim 3, whiCh further includes: A. means for detecting when all of the bits of a character have been transmitted over an input line and assembled into the character assembly word associated therewith; and B. means controlling the processing of an assembled character, said means including

Claim 27

The system defined in claim 9, wherein said clock pulses are generated at a rate of n times the rate at which character bits are transmitted over the input lines, where n is an odd number greater than 1, said count word portion of said line status words is repeated incremented to a count of n and reset during a character transmission over the associated input line, and said assembly means operates to assemble a character bit each time a count word portion reaches n/2 + 1/2 .

Claim 28

The system defined in claim 10, wherein n equals 5.

Claim 29

The system defined in claim 9, wherein each said line status word also includes a coded line number of the input line associated therewith, and said clock pulse responsive means includes

Claim 30

The system defined in claim 9, which further includes: A. a storage element associated with each input line, said element

Claim 31

The system defined in claim 9 wherein each input line has a specified rate at which it transmits data characters, the input lines with substantially the same transmission rates being categorized in a group, said system additionally comprising one of said clocks and one of said clock responsive means for each separate group of input lines.

Claim 32

In a system for assembling character bits of data characters randomly transmitted in serial bit format over a plurality of lines including means cyclically operable for sampling the plurality of input lines in succession and for assembling the character bits and means for detecting when all of the bits of a character have been transmitted over an input line and assembled into a character assembly word associated therewith, means for controlling the processing of an assembled character including: A. a load distribution register loaded at the beginning of each sampling cycle with a number which is a predetermined fraction of the total number of input lines to be sampled in a sampling cycle, and B. means for decrementing said load distribution registers each time an assembled character is processed during a sampling cycle, said means inhibiting the processing of additional assembled characters during the sampling cycle in progress when the load distribution register count is zero.

Claim 33

In a system for assembling character bits of data characters randomly transmitted in serial bit format over a plurality of lines including means cyclically operable for sampling the plurality of input lines in succession and for assembling the character bits and means for detecting when all of the bits of a character have been transmitted over an input line and assembled into a character assembly word associated therewith, means for controlling the processing of an assembled character including: A. a load distribution register loaded at the beginning of each sampling cycle with a number which is a predetermined fraction of the total number of input lines to be sampled in a sampling cycle, and B. means for decrementing said load distribution registers each time an assembled character is processed during a sampling cycle, said means inhibiting the processing of additional assembled characters during the sampling cycle in progress when the load distribution register count is zero.

Claim 34

The system as defined in claim 15 wherein additional assembled characters, not processed during one sampling cycle because said decrementing and inhibiting means prevents further assembly, are processed during subsequent sampling cycles.

Claim 35

The system defined in claim 15 including a storage element associated with each input line, said element being conditioned to designate, during subsequent sampling cycles, those character assembly words which contain assembled characters awaiting processing.