US3721835A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hardlimiter, automatic symmetry circuit
Assignee: United States Department of the Navy
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Filing: 1972-01-05
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Granted: 1973-03-20
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Expires: 1992-01-05
Abstract
Abstract A hardlimiter automatic symmetry control circuit having an amplified input and a dual differential line driver producing logic output with a symmetry sensing circuit in a negative feedback from the dual driven logic output to the amplifier input to convert output logic signals to a direct current (D.C.) voltage of a polarity that is solely a function of the output symmetry to control the amplifier to maintain symmetry to logic signals in the output.
Inventors
- 👤 W Hess
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:24
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K5/082; H03K5/086; H03K5/088; H03G; H03G11/00; H03G11/02
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
172 words
A hardlimiter automatic symmetry control circuit comprising: first and second differential amplifiers each having two inputs and an output, one input of said first differential amplifier adapted to be coupled to a frequency signal and said output of said first differential amplifier coupled to one input of said second differential amplifier, a line driver having an input coupled to said differential amplifier output and having two outputs, said line driver generating binary logic in the ''''1'''' and ''''0'''' states on said outputs in accordance with the time elapse for each positive and negative voltage swing of said frequency signal; a symmetry sensing circuit having two inputs coupled respectively to said two line driver outputs and an output coupled to the other said input of said first differential amplifier for generating a direct current output voltage of a polarity proportional to the predominant time of the logic in said ''''1'''' and ''''0'''' states whereby said first differential amplifier will be adjusted to bring the frequency signal crossover points to a symmetrical time state.
Claim 2
Dependent Claim
172 words
A hardlimiter automatic symmetry control circuit comprising: first and second differential amplifiers each having two inputs and an output, one input of said first differential amplifier adapted to be coupled to a frequency signal and said output of said first differential amplifier coupled to one input of said second differential amplifier, a line driver having an input coupled to said differential amplifier output and having two outputs, said line driver generating binary logic in the ''''1'''' and ''''0'''' states on said outputs in accordance with the time elapse for each positive and negative voltage swing of said frequency signal; a symmetry sensing circuit having two inputs coupled respectively to said two line driver outputs and an output coupled to the other said input of said first differential amplifier for generating a direct current output voltage of a polarity proportional to the predominant time of the logic in said ''''1'''' and ''''0'''' states whereby said first differential amplifier will be adjusted to bring the frequency signal crossover points to a symmetrical time state.
Claim 3
Dependent Claim
22 words
A hardlimiter as set forth in claim 1 wherein said second differential amplifier has its other input coupled to a zero potential.
Claim 4
Dependent Claim
68 words
A hardlimiter as set forth in claim 2 wherein said symmetry sensing circuit includes a pair of emitter grounded transistors and an operational amplifier with the base electrode of each transistor coupled respectively to one each of said two line driver outputs and the collectors coupled respectively to each of two inputs of said operational amplifier, the output of said operational amplifier being said symmetry sensing circuit output.
Claim 5
Dependent Claim
91 words
A hardlimiter as set forth in claim 3 wherein said pair of emitter grounded transistors are each collector coupled through a resistor to said operational amplifier input and through Resistors to a voltage source, one operational amplifier input being coupled in parallel through a resistor and a capacitor in a feedback circuit from the output and the other operational amplifier input being coupled in parallel through a resistor and a capacitor to a zero potential, all said resistors being of values to accurately determine crossover voltage changes of said frequency signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-19 | 1976-09-18 | 1977-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-19 | 1980-09-18 | 1981-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-19 | 1984-09-18 | 1985-03-20 | $7700.00 | Window Closed / Lapsed |