Method and apparatus for displaying and/or recording measured values

Claim 5

The method of claim 1 wherein said measuring location identifying values are running time values of the measuring period Lm.

Claim 6

Method as defined in claim 2 wherein the write-in timing frequency for the memory circuit is entirely independent of the read-out timing frequency as regards frequency and synchronization, the read-out timing frequency is optimally adapted to the available devices utilized for compiling, evaluating, displaying and/or recording the measured values (mi), while the write-in timing frequency is oriented only to the conditions of the measured value compilation during the measuring periods (Lm).

Claim 7

The method as defined in claim 3 wherein the measuring period (Lm) and the display period (Td) are started independent of one another.

Claim 8

The method as defined in claim 1 wherein the sequence in which the display locations (ld) are available during the display period (Td) is reversed with respect to the sequence of the measuring intervals (lm) during the measuring period (Lm).

Claim 9

The method of claim 1 including the step of generating and recording an indication representative of the quality of the measured value information according to a given criterion stored in each address of the memory.

Claim 10

The method as defined in claim 6 wherein the repetition frequency of a measured value (mi) is used as the quality criterion and including the steps of: comparing each new measured value (mi) before it is written into the memory circuit, with the comparable measured value (mi) stored therein; and, in the event of coincidence within a given tolerance range (tol) between the compared values, changing the value of the indications representative of the quality of the measured value information (hereinafter referred to as the comparison value signal Il) stored in the memory to an upgraded value which, compared to the previously available value, represents, per definition, an improved value.

Claim 11

The method as defined in claim 7 wherein new measured values (mi) which do not coincide, within a given tolerance range (tol), with already stored older measured values (mi) are written into an available free location in the memory and are provided with a minimum comparison value signal (Ilmin).

Claim 12

The method as defined in claim 8 wherein new measured values (mi) are compared with previously recorded measured values (mi) which appeared in the preceding adjacent measuring period (Lm) for the same position identifying values (Mi).

Claim 13

The method as defined in claim 8 wherein new measured values (mi) are compared with previously recorded measured values (mi) which appeared in the same measuring period (Lm) but for the previous Position identifying value (Mi-1).

Claim 14

The method as defined in claim 8 wherein each new measured value (mi) is compared only for coincidence within the given tolerance range (tol) with any measured value (mi) already stored in the memory.

Claim 15

The method as defined in claim 6 wherein, in the event of coincidence, within a given tolerance range (tol) between an older stored measured value (mi) and a newer measured value (mi), in addition to upgrading the comparison value (Il), the older stored measured value (mi) is upgraded by writing the newer measured value in the associated memory address location in place of the older previously stored measured value.

Claim 16

The method as defined in claim 12 wherein stored measured values (mi) which are already associated with a given optimum comparison value (Ilopt) are no longer upgraded when a new confirmation by new measured values (mi) occurs within the given tolerance range (tol).

Claim 17

The method as defined in claim 13 including, during the writing of information into the memory, providing and storing a marker (n) for each memory location in which a measured value (mi) from measuring period (Lm) being processed has been written.

Claim 18

The method as defined in claim 14 wherein, after the measured values (mi) in all of the memory locations of the memory have been tested for comparison with measured values (mi) determined in a measuring period (Lm) and before the initiation of the processing of new measured values from a measuring period (Lm+1): each comparison value (Il) associated with a memory location not provided with a marker (n) is reduced in value by one unit, and all of the information, e.g. measured value (mi) and comparison value (Il), in each memory location which is provided with a comparison value (Il) which corresponds to the minimum comparison value (Ilmin) and does not have a marker (n) is erased so that from now on the respective memory location is available for new measured values (mi), and each of the markers (n) is erased.

Claim 19

The method as defined in claim 7 wherein the new measured value is written into a memory location of the memory when coincidence occurs between an older stored measured value and a new measured value (mi), and measured values (mi) of consecutive measuring periods (Lm) which coincide a predetermined number of times are erased.

Claim 20

The method as defined in claim 7 wherein: during the read out of the memory in a display period (Td), the comparison values (Il) are detected and only measured values (mi) stored in the memory circuit which are associated with a predetermined optimum comparison value (Ilopt) obtained from a sufficient number of repeated confirmations of successively arriving comparable measured values (mi) are read out upon comparison of the values DK and Mi, so that the reading out of a particular measuring value (mi) when the display marker implement has reached that display section (ld) within the display range (Ld) which, with the given display scale, represents a true-to-scale representation of the present measured value (mi) without there existing a direct connection with the preceding process of compiling the measured values.

Claim 21

The method as defined in claim 2 wherein the entire course of the measured values (mi) is quantized over the independent variable (P) for each measuring period (Lm) and the measured values (mi) are written into the memory utilizing the running time values (Mi) as address values.

Claim 22

The method as defined in claim 2 wherein only the portion of the course of the measured values (mi) which is of interest is quantized over the independent variable (P) for each measuring period (Lm) and the measured values (mi) are written into the memory utilizing the running time values (Mi ) as address values, and wherein the running time values defining the beginning and the end of the course portion of interest are simultaneously written into the memory with the associated measured value (mi) as auxiliary data (Zi).

Claim 23

The method as defined in claim 19 wherein only the running time values defining the beginning and end of each succession of measured values (mi) of interest within one measuring period (Lm) are written into the memory.

Claim 24

The method as defined in claim 18 wherein only the running time value (Mi) at the first appearance of a typical event is considered as the applicable measured value (mi) for each measuring period (Lm).

Claim 25

The method as defined in claim 2 wherein in order to provide for a variation of range and/or scale of the display of the measured values (mi) within the display range (Ld), a selectable number of running-time values (Mi) is associated to a selectable number of display location values (DK) which represent the respective available display range (Ld).

Claim 26

The method as defined in claim 22 wherein with a constant quantization of the measuring period (Lm) and of the display period (Td) in scale and/or range the variation is accomplished by varying the association required between the values Mi and DK for read-out and display by means of a switchable digit comparator.

Claim 27

The method as defined in claim 22 wherein the variation in scale and/or measuring range is accomplished by varying the measuring timing frequency, and thus the timing of the quantization of the measuring period (Lm) while maintaining a constant read-out timing frequency, and thus constant quantization of the display range (Ld), and the same association between the values Mi and DK.

Claim 28

The method as defined in claim 22 wherein the measuring timing frequency is not constant during a measuring period (Lm).

Claim 29

The method as defined in claim 25 wherein the measuring timing frequency varies at a logarithmically decreasing frequency.

Claim 30

The method as defined in claim 1 wherein the steps of writing the measured values (mi) into the memory and of reading out the measured value (mi) for reproduction, occur in an alternating sequence, and wherein the reading-out of the measured values (mi) from the memory circuit is rigidly coupled with the reproduction along the display range (Ld).

Claim 31

The method as defined in claim 1 wherein the method is utilized on a surveying vessel for measuring, compiling and reproducing measured values in an echo sounding arrangement, and wherein the quantization density of the measuring period (Lm), i.e. the number of measuring intervals (lm), is varied in a sense opposite to the momentary lifting movement of the surveying vessel.

Claim 32

Apparatus for compiling, evaluating, displaying and/or recording, preferably for displaying and/or recording in the form of a columnar arrangement, measured values (mi) obtained during a measuring period (Lm) within a sequence of measuring periods and dependent on a given independent variable (P), wherein the measuring period (Lm) and the displaying and/or recording period (hereinafter uniformly called the display period Td) take place independent of one another, so that the display and/or recording can take place, if required, at another location and at another time than where the measured values were compiled, comprising: means for quantizing the independent variable (P) of the measuring period (Lm) and providing a running time digital identifying value (Mi, where i 0-p) for each of the resulting measuring intervals (lm); means for quantizing the measured values (mi) of a measuring period (Lm) which has been started at any desired Point in time with respect to the momentary conditions of a display period (Td); means for writing the quantized measured values (mi) from each measuring period (Lm) into a memory circuit utilizing the identifying values Mi as memory address values (Ai); display means; means for quantizing a given display range (Ld) of said display means providing a digital and display location value (DK, where K 0-q) for each of the resulting display sections (ld); means for comparing each consecutive digital display location value DK occurring during a display period (Td) started at any desired point in time with respect to the momentary conditions of a measuring period (Lm); with the identifying values Mi stored in said memory circuit and for providing an output signal whenever a predetermined association exists between a value Dk and the single value Mi corresponding thereto; and read-out means, responsive to the output signals from said means for comparing, for reading out the information stored in the memory location having the memory address corresponding to the just compared digital value Mi and for transmitting the read-out information to said display means for display in the associated display location (ld).

Claim 33

Apparatus for compiling, evaluating, displaying and/or recording, preferably for displaying and/or recording in the form of a columnar arrangement, measured values (mi) obtained during a measuring period (Lm) within a sequence of measuring periods and dependent on a given independent variable (P), wherein the measuring period (Lm) and the displaying and/or recording period (hereinafter uniformly called the display period Td) take place independent of one another, so that the display and/or recording can take place, if required, at another location and at another time than where the measured values were compiled, comprising: means for quantizing the independent variable (P) of the measuring period (Lm) and providing a running time digital identifying value (Mi, where i 0-p) for each of the resulting measuring intervals (lm); means for quantizing the measured values (mi) of a measuring period (Lm) which has been started at any desired Point in time with respect to the momentary conditions of a display period (Td); means for writing the quantized measured values (mi) from each measuring period (Lm) into a memory circuit utilizing the identifying values Mi as memory address values (Ai); display means; means for quantizing a given display range (Ld) of said display means providing a digital and display location value (DK, where K 0-q) for each of the resulting display sections (ld); means for comparing each consecutive digital display location value DK occurring during a display period (Td) started at any desired point in time with respect to the momentary conditions of a measuring period (Lm); with the identifying values Mi stored in said memory circuit and for providing an output signal whenever a predetermined association exists between a value Dk and the single value Mi corresponding thereto; and read-out means, responsive to the output signals from said means for comparing, for reading out the information stored in the memory location having the memory address corresponding to the just compared digital value Mi and for transmitting the read-out information to said display means for display in the associated display location (ld).

Claim 34

The apparatus as defined in claim 29 including a control clock pulse generator; and wherein said memory circuit comprises a closed ring-type shift register having a number of shift stages at least equal to the maximum number of identifying values (Mi) i.e., the number of measuring intervals (lm) occurring within one measuring period (Lm), the timing of said shift register being controlled by the clock pulses from said clock pulse generator.

Claim 35

The apparatus as defined in claim 30 wherein said display means includes drive means for moving the marking means of said display means in a uniform manner over the display range in the direction of the recording of the measured values (mi) of a measuring period (Lm); and wherein said means for quantizing a given display range includes means for emitting a series of display location pulses (Id) whose number corresponds to the momentary position of said marking means within said display range, and a digital counter for counting said display location pulses and whose count represents the display location values DK.

Claim 36

The apparatus as defined in claim 31 wherein said display means is a conventional recorder having drive means mechanically coupled to a writing stylus which serves as said marking means, said stylus being coupled to said means for emitting a series of display location pulses.

Claim 37

The apparatus defined in claim 32 wherein said drive means for said writing stylus is a motor which when actuated advances said stylus in a continuous manner over said display range; and wherein said means for emitting a series of display location pulses comprises a pulse disc connected to the motor shaft for rotation therewith and a stationary pick-off.

Claim 38

The apparatus as defined in claim 32 wherein said means for emitting a series of display location pulses is an electronic location pulse generator; and wherein said drive means for said writing stylus is a stepping motor, said stepping motor being excited by the output pulses of said location pulse generator.

Claim 39

The apparatus as defined in claim 31, including a freely running clock pulse generator for providing a series of central control clock pulses said control clock pulses simultaneously determining the write-in timing for said memory circuit and effecting the quantization of the measuring period (Lm).

Claim 40

The apparatus as defined in claim 35 wherein said freely running clock pulse generator provides said central control clock pulses at a constant repetition frequency; wherein said means for quantizing the independent variable of the measuring period (Lm) includes a second digitAl counter responsive to said central control clock pulses for counting same to provide said values Mi and means for resetting and releasing said second digital counter at the beginning of each measuring period; and wherein said means for comparing the display location values DK and the identifiying values Mi comprises at least one translator operating as a digital number comparator.

Claim 41

The apparatus as defined in claim 36 wherein said translator is a binary-decimally operating digital number comparator circuit.

Claim 42

The apparatus as defined in claim 36 including means for varying the predetermined association between said values Mi and DK at which said means for comparing emits an output signal, whereby the scale and/or range of the display may be controlled.

Claim 43

The apparatus defined in claim 36, including an adjustable pulse frequency divider connected between the output of said freely running clock pulse generator and the input of said second digital counter, whereby the scale of the display may be varied by changing the frequency of the pulses counted by said second digital counter and without any change in the mode of operation of said translator.

Claim 44

The apparatus defined in claim 36 including pulse frequency reducing means connected between the output of said freely running clock pulse generator and the input of said second digital counter for cutting out individual pulses of said series of central control clock pulses at a logarithmically increasing rate, whereby a logarithmic display can be presented without any change in the mode of operation of said translator.

Claim 45

The apparatus as defined in claim 36 including preprogrammed circuitry means for varying the scale of the display by varying the relationship between the digital values DK and Mi.

Claim 46

The apparatus defined in claim 41 including circuit means responsive to the measured value information for stopping the counting of said second digital counter during a measuring period.

Claim 47

The apparatus defined in claim 42 wherein said apparatus is utilized in an echo sounding system and wherein said circuit means for stopping the counting of said digital counter is connected to the receiver amplifier of said system and is responsive to a received bottom echo signal (Be) to stop said counter, whereby the value Mi in said counter also serves as the measured value mi.

Claim 48

The apparatus defined in claim 43 wherein said circuit means for stopping the counting of said second digital counter includes: a gate connected between the output of said freely running clock pulse generator and the input of said second digital counter; and switch means for controlling said gate to selectively cause the stopping of the counting of said second digital counter either upon the receipt of said bottom echo signal or upon the output of said second digital counter reaching a predetermined count.

Claim 49

The apparatus of claim 44 wherein said switch means automatically causes the resetting and the releasing of said second digital counter to begin a new measuring period after transfer of the value Mi into said memory circuit.

Claim 50

The apparatus of claim 43 further comprising means including an integrating and threshold value circuit for controlling the amplification factor of said receiving amplifier in accordance with the momentary occupation density of the memory location of said memory circuit.

Claim 51

The apparatus defined in claim 31 including auxiliary data input means for supplying digitally coded auxiliary data (Zi) associated with the measured values (mi) to the input of said memory circuit for storage therein together with the associated measured values.

Claim 52

The apparatus as defined in claim 32 wherein said recorder is an echograph with a rotating stylus band on which said writing stylus is connected, and wherein said stylus band includes said means for emitting said series of display location pulses (Id).

Claim 53

Apparatus as defined in claim 30 wherein said means for quantizing a given display period comprises means coupled to the said writing means and responsive to the relative position thereto for directly emitting coded position-dependent display location parameters (DK).

Claim 54

The apparatus defined in claim 31 wherein each measured value stored in the memory location is provided with an additional indication representative of the quality of the stored data; and wherein said apparatus further includes: means for comparing each new measured value (mi), before it is written into the memory circuit, with the comparable measured value (mi) stored therein, and (1) in the event of coincidence within a given tolerance range (tol) between the compared values, changing the value of the indications representative of the quality of the measured value information (hereinafter referred to as the comparison value signal Il) stored in the memory to an upgraded value, and (2) in the event of no coincidence within a given tolerance range (tol) between the compared values, causing the new measured value to be stored in an available free location in said memory circuit with a minimum comparison value (Ilmin).

Claim 55

The apparatus defined in claim 50 wherein said means for comparing each new measured value before it is written into the memory circuit includes: a digital comparator means having one input connected to the read-out access of said memory circuit, wherein the data is being continuously shifted in a rapid sequence, and a second input connected in the input path for the input data to the memory circuit; an adjustable tolerance signal generating means connected to a further input of said digital comparator means for setting the coincidence tolerance range, said comparator means having a first output connected to the write-in access of said memory circuit and a second output, said comparator means providing an output signal at said second output whenever information is to be written into the particular memory location then present at read-out access of said memory means; and an evaluator circuit, having one input connected to said second output of said comparator means, and a second input connected to said memory means so as to read the stored comparison value signals (Il), said evaluator circuit being responsive to a signal at said one input thereof to upgrade the value of the comparison value signal being read and change the value thereof in the memory circuit location.

Claim 56

The apparatus of claim 51 wherein upon coincidence between two compared values, said comparator means causes the new measured value to be written into the memory circuit in place of the previously stored value.

Claim 57

The apparatus of claim 51 wherein said evaluator means is a forward and backward counting circuit and wherein said evaluator means causes a marker (n) to be stored in each memory location in which information for the measuring period (Lm) being processed is written and said marker to be erased during a subsequent cycle of the data in said memory circuit before the measured information from the next measuring period (Lm+1) is processed; and wherein said apparatus further includes a cleaning circuit means which is responsive to said stored markers during said subsequent cycle for causing said evaluator means to downgrade the comparison value signal (Il) associated with each memory location not provided with a marker (n).

Claim 58

The apparatus defined in claim 53 wherein said evaluator means is a forward and backward counting counter circuit according to the Gray code for numerical values between 0 and 3 for the comparison values (Il).

Claim 59

The apparatus defined in claim 53 including a transfer circuit and at least one intermediate memory connected in series between said second input of said comparator means and the data inputs for the information to be stored, each intermediate memory having a number Of flipflop stages corresponding to the maximum number of bits for the total input data (mi, Mi, Zi) to be stored in a memory location once per measuring period (Lm).

Claim 60

The apparatus defined in claim 50 including means for passing only stored values of Mi which are associated in the memory with an optimum comparison value (Ilopt) to said means for comparing each consecutive digital location value DK with the identifying values Mi during a display period.

Claim 61

The apparatus defined in claim 31 wherein said drive means for said display means has its sequence of movement selected so that said marking means is disposed within one display section (ld) at least during one cycle of the information (mi, Zi) through said memory circuit.

Claim 62

The apparatus defined in claim 36 wherein said drive means for said display means has its sequence of movement selected so that said marking means is disposed within one display section (ld) at least during one cycle of the information (mi, Zi) through said memory circuit; and wherein the said read-out means includes a gate responsive to an output signal from said translator, and a digital/analog converter for converting the digital signals read out of said memory circuit to analog signals for display.

Claim 63

The apparatus defined in claim 58 wherein said digital/analog converter comprises a writing voltage source, the output value of which controls the intensity of the display mark representing the measured value.

Claim 64

The apparatus defined in claim 59 wherein the information being measured is the time for the return of the echo of a transmitted pulse; wherein said display means is a recording echograph and wherein the output signal of said writing voltage source is connected via said gate to the contact rail for the writing stylus of said echograph to provide a mark at the appropriate display location.

Claim 65

The apparatus defined in claim 39 wherein said second digital counter is a combination of a primary counter and a carry counter connected thereto which has a lesser number of bit locations than said primary counter, said primary and carry counters having parallel outputs.

Claim 66

The apparatus defined in claim 61 wherein said primary counter has a number of stages sufficient to count a fraction of the values Mi of a measuring period Lm, measured by the quantization into measuring intervals corresponding to the desired resolution, and said primary counter starting its count over again during a measuring period (Lm) each time a carry pulse (Ic) has been transmitted to the carry counter.

Claim 67

The apparatus defined in claim 62 further including a digital comparator means having one input connected to the parallel outputs of said primary counter and a second input connected to said memory for comparing each new measured value obtained during a measuring period (Lm) with a corresponding value previously stored in said memory circuit, and for causing values for which no coincidence occurs to be written in a new location of said memory circuit; a partial section signal generating means for selectively providing a digital signal, which is coded in the same code as the digital code utilized in said primary and carry counters, having a value representative of a selected partial section of the measuring period (Lm); signal inverting means having parallel outputs and its input connected to the output of said partial section signal generating means; a digital adder for adding each of the outputs of said inverting means, with the exception of the output representing the lowest order bit, with the corresponding output of said carry counter; and an AND gate having its inputs connected to the outputs of said adder and its output connected to an enabling input of said comparator, whereby only measured values occurring within the selected partial section of the measuring period will be compared and stOred.

Claim 68

The apparatus defined in claim 63 wherein said adder is provided with an additional adder stage the output of which is connected to said comparator and represents the highest order bit of said primary counter, the inputs of said additional adder stage being connected to the output of said inverting means representing the lowest order bit and the output of said primary counter representing the highest order digit, whereby the output of said primary counter representing the highest order digit is not directly coupled to said comparator means bit only via said additional adder stage.

Claim 69

Apparatus as defined in claim 63 wherein said carry counter is provided, in addition to the number of bit locations required to count out the partial sections of the entire measuring period, with a further, highest-value bit location for producing a final carry pulse (Icc1) at the output thereof after passage of the last partial section of the measuring period (Lm); and further including switching circuit means responsive to an input signal thereto for stopping and resetting said primary and carry counters, said output of said highest-value bit location of said carry counter being coupled to the input of said switching circuit means.

Claim 70

The apparatus defined in claim 65 wherein said output of said highest-value bit location of said carry counter is connected with the input of said switching circuit means via an OR gate; wherein said adder provides a carry pulse (Icc2) at a carry output at the end of a partial section selected by means of the signal from said partial section signal generator; and wherein said carry output of said adder is connected to the other input of said OR gate.

Claim 71

The apparatus defined in claim 58 including a range marker signal generating means, the output of said range marker signal generating means being coupled to said marking means via said gate to cause an indication representative of the particular display range being utilized to appear in the display.

Claim 72

The apparatus defined in claim 63 including a range marker signal generating means, the output of said range marker signal generating means being coupled to said marking means via said gate to cause an indication representative of the particular display range being utilized to appear in the display; and wherein said range marker signal generating means has its input coupled to the output of said partial section signal generating means, whereby said range marker signal generating means automatically causes an indication of the selected partial section of the measuring period.

Claim 73

The apparatus defined in claim 68 including a blocking key for temporarily blocking the function of said range marker signal generating means during a display period.

Claim 74

The apparatus defined in claim 47 wherein said apparatus is utilized for measuring the returned echoes of transmitted signals; wherein said auxiliary data input means includes a fundamental frequency discriminator which is connected between the output of an echo signal receiver and the input of an auxiliary data signal generating means for providing auxiliary data signals to identify different frequency based measured values (mi) and to identify measured values (mi) which have different fundamental frequencies in their bottom echo signals (Be, Be1, ...).

Claim 75

The apparatus defined in claim 59 wherein said apparatus is utilized in an echo sounding system; wherein said gate has a bistable characteristic; and further including a backward counting digital counter means for storing a value representative of the return echo time; means for supplying said backward counting digital counter means with said value representative of the return echo time at the beginning of a display period; said backward counting digital counter means being responsive to the output signal from said translator to close said gate and to begin its backward count, and to open said gate when it has counted out the value momentarily stored therein.

Claim 76

The apparatus defined in claim 71 wherein said means for supplying said backward counting digital counter means includes a further digital counter means for counting the pulses from said free running control clock pulse generator, and means for stopping the count of said further digital counter upon receipt of a returned echo pulse whereby the value stored in said further digital counter is the measured value (mi).

Claim 77

The apparatus defined in claim 59, including an amplitude coder means for providing a coded output signal proportional to the amplitude of a measured value input signal to said apparatus; and wherein said writing voltage source is responsive to the output signal from said amplitude coder means to vary the intensity of the output thereof.

Claim 78

The apparatus defined in claim 39 wherein said apparatus is utilized in an echo sounding system; wherein the value Mi present in said second digital counter at the time of receipt of an echo from a transmitted signal is the measured value (mi); and wherein an adjustable range preselector means is provided for furnishing a digital value equal to a preselected starting identifying value (Ma) at the beginning of each measuring period (Lm); and means for transferring said value Ma to said second digital counter at the beginning of each measuring period.

Claim 79

The apparatus defined in claim 39 wherein said apparatus is utilized in an echo sounding system; wherein the transmission of a signal by means of a signal transmitter initiates the measuring period (Lm) and the starting of the counting by said second digital counter; wherein the value in said second digital counter upon receipt of an echo of a transmitted signal is proportional to the travel time of said transmitted signal; and wherein said apparatus further includes means for triggering said signal transmitter whenever said second counter reaches a predetermined count following the beginning of a measuring period (Lm).

Claim 80

The apparatus defined in claim 31 wherein said apparatus is utilized in an echo sounding system on a surveying vessel; wherein the transmission of a signal by means of a signal transmitter initiates the measuring period (Lm) and the starting of the counting by said second digital counter; wherein the value in said second digital counter upon receipt of an echo of a transmitted signal is proportional to the travel time of said transmitted signal; and wherein said apparatus further includes means for triggering said signal transmitter in accordance with the environmental conditions on said surveying vessel to provide optimum conditions for the transmission.

Claim 81

The apparatus defined in claim 76 wherein said means for triggering said signal transmitter comprises an inclinometer.

Claim 82

The apparatus defined in claim 76 wherein said means for triggering said signal transmitter comprises a lift accelerometer for said surveying vessel.

Claim 83

The apparatus defined in claim 31 wherein said apparatus is utilized in an echo sounding system on board a surveying vessel; wherein said display means is an echograph having a marking means in the form of a writing stylus which traverses the record on said echograph in a uniform manner and transverse to the longitudinal direction of said record; and wherein said apparatus further includes a first transmitting means for echo soundings in shallow water; a stylus end of travel contact means on said echograph for producing a signal when said writing stylus has reached the end of a display range during each display period, said first transmitting means being responsive to the signal produced by said end of travel contact means to transmit a signal; a first receiver for the echoes of signals transmitted by said first transmitting means, the output of said first receiver being coupled to the input of said memory circuit for storing the received bottom echo signals in timed sequence in adjacent memoRy locations; and a start of travel contact means on said echograph for producing a signal when said writing stylus begins its travel over the display range at the beginning of each display period, said read-out means being responsive to the signal from said start of travel contact means to read out the information stored in said memory circuit and feed the same to said writing stylus, whereby the speed of the drive means for said writing stylus may be set at an optimum fast speed for displaying information from shallow water echo soundings.

Claim 84

The apparatus defined in claim 79 including: a second transmitter means and a second receiver means for deep water echo soundings; and an operational mode switch for selectively disconnecting said end of travel contact means and said start of travel contact means from said first transmitter means and the output of said memory circuit, respectively, and for connecting said start of travel contact means to said second transmitter means and the output of said second receiving means to said writing stylus.

Claim 85

The apparatus defined in claim 80 including an analog/digital converter connected between the input of said memory and the output of said first transmitter means and a digital/analog converter connected between the output of said memory circuit and said operational mode switch.