Scanner circuit

Claim 2

A scanner circuit comprising: a counter circuit for counting clock pulses applied thereto; decoder circuit means coupled to said counter circuit for providing sequential scanning pulses; first circuit means for stopping said counter circuit in response to a current pulse in said decoder circuit in response to a scanning pulse; a memory circuit; second circuit means responsive to a control signal for applying a count to said counter circuit corresponding to a count stored in the memory circuit; third circuit means responsive to a control signal for applying a count to said memory circuit corresponding to a count stored in the counter circuit, and control circuit means enabling said counter circuit to begin a preset number of successive counting cycles in a scanning sequence and applying a control signal to the second circuit means prior to the first counting cycle in the sequence and applying a control signal to the third circuit means after the counter has been stopped by the first circuit means during the first counting cycle.

Claim 3

A scanner circuit comprising: counter circuit means for counting clock pulses applied thereto, to produce sequential scanning pulses; first circuit means for stopping said counter circuit in response to a signal condition caused by any of said scanning pulses; control circuit means for enabling said counter circuit means to start a preset number of successive counting cycles in a scanning sequence; memory circuit means; second circuit means for applying a count to said counter circuit corresponding to a count stored in said memory circuit means prior to the start of the first counting cycle in the scanning sequence, and third circuit means for applying a count to said memory circuit means corresponding to a count in said counter circuit means when the counter circuit means has been stopped by said first circuit means during the first counting cycle in the scanning sequence.

Claim 4

A scanner circuit comprising: counter circuit means for counting clock pulses applied thereto, to produce sequential scanning pulses; first circuit means for stopping said counter circuit in response to a signal condition caused by any of said scanning pulses; control circuit means for enabling said counter circuit means to start a preset number of successive counting cycles in a scanning sequence; memory circuit means; second circuit means for applying a count to said counter circuit corresponding to a count stored in said memory circuit means prior to the start of the first counting cycle in the scanning sequence, and third circuit means for applying a count to said memory circuit means corresponding to a count in said counter circuit means when the counter circuit means has been stopped by said first circuit means during the first counting cycle in the scanning sequence.

Claim 5

A scanner circuit as defined in claim 2 wherein: said counter circuit means includes a decoder circuit having a plurality of output circuits for providing the successive scanning pulses and a continuous output on one of said output circuits when said counter circuit is stopped that corresponds to the count in said counter circuit means.

Claim 6

A scanner circuit as defined in claim 3 including: fourth circuit means for providing an output signal on one of a first plurality of lines corresponding to the count in said counter circuit means when said counter circuit means is stopped at the end of a plurality of counting cycles of said scanning sequence, and fifth circuit means for providing an output signal on one of a second plurality of lines corresponding to the count in said counter circuit means when said counter circuit means is stopped at the end of at least the last counting cycle of said scanning sequence.

Claim 7

A scanner circuit as defined in claim 1 wherein: said second means includes a latching circuit that enables the transfer of counts from the memory circuit means to said counter circuit means only once during each scanning sequence, and said third circuit means includes a latching circuit that enables the transfer of counts from the counter circuit means to the memory circuit means only once during each scanning sequence.

Claim 8

A scanner circuit as defined in claim 2 including: circuit means for detecting the number of times said counter circuit means in a counting cycle has reached a preset count and to produce an output signal whEn said preset count has been reached a predetermined number of times.

Claim 9

A scanner circuit as defined in claim 6 wherein: said detecting circuit means resets the counter circuit means when said preset count is reached.

Claim 10

A scanner circuit as defined in claim 7 wherein: said detecting circuit means produces an output signal when the preset count in the first counting cycle in a scanning sequence is reached a second time.

Claim 11

A scanner circuit as defined in claim 8 wherein: said detecting circuit means produces a second output signal when the preset count in the first counting cycle in a scanning sequence is reached a third time.

Claim 12

A scanner circuit comprising: a counter circuit means for counting clock pulses applied thereto; a decoder circuit means coupled to said counter circuit means for providing scanning pulses in sequential order on a plurality of output lines when the counter circuit is counting, and when the counter circuit is stopped providing a continuous signal on one of the output lines corresponding to the count at which the counter stopped; circuit means responsive to be enabled by a first control signal for applying the scanning pulses to a first plurality of output circuits; circuit means for stopping said counter circuit means in response to a signal condition caused by any of the scanning pulses on the first plurality of output circuits; circuit means responsive to be enabled by a second control signal for applying signals from said scanner output lines to any one of a second plurality of output circuits; circuit means responsive to be enabled by a third control signal for applying signals from said scanner output lines to any one of a third plurality of output circuits; control circuit means coupled to said counter circuit means for enabling said counter circuit means to start a preset number of successive counting cycles in a scanning sequence, and circuit means for applying said first control signal while said counter circuit means is counting, for applying said second control signal at the end of preset number of successive number of counting cycles in a scanning sequence including the first counting cycle, and for applying said third control signal at the end of at least the last counting cycle in a scanning sequence.

Claim 13

A scanner circuit comprising: a counter circuit means for counting clock pulses applied thereto; a decoder circuit means coupled to said counter circuit means for providing scanning pulses in sequential order on a plurality of output lines when the counter circuit is counting, and when the counter circuit is stopped providing a continuous signal on one of the output lines corresponding to the count at which the counter stopped; circuit means responsive to be enabled by a first control signal for applying the scanning pulses to a first plurality of output circuits; circuit means for stopping said counter circuit means in response to a signal condition caused by any of the scanning pulses on the first plurality of output circuits; circuit means responsive to be enabled by a second control signal for applying signals from said scanner output lines to any one of a second plurality of output circuits; circuit means responsive to be enabled by a third control signal for applying signals from said scanner output lines to any one of a third plurality of output circuits; control circuit means coupled to said counter circuit means for enabling said counter circuit means to start a preset number of successive counting cycles in a scanning sequence, and circuit means for applying said first control signal while said counter circuit means is counting, for applying said second control signal at the end of preset number of successive number of counting cycles in a scanning sequence including the first counting cycle, and for applying said third control signal at the end of at least the last counting cycle in a scanning sequence.

Claim 14

a scanner circuit as defined in claim 10 wherein: each of said three circuit means responsive to the first, second and third control signals include a plurality of gating circuits, one for each of its plurality of output circuits; said first control signal comprises clock pulses for enabling the gating circuits in the circuit means responsive to the first control signal in synchronism with the counting rate of said counter circuit means, and said second and third control signals, when applied, are continuous signals.

Claim 15

A scanner circuit as defined in claim 10 wherein: said circuit means for applying said first, second and third control signals applies the second control signal at the end of successive counting cycles and is responsive to a fourth control signal to apply the third control signal at the end of at least one counting cycle subsequent to the receipt of the fourth control signal.

Claim 16

A scanner circuit comprising: counter circuit means for receiving counting pulses to provide sequential scanning pulses; circuit means for stopping said counter circuit in response to a signal condition caused by any of the scanner pulses, and control circuit means responsive to input signals for enabling said counter to start a preset number of successive counting cycles in a scanning sequence wherein the first counting cycle of a scanning sequence starts at the count at the end of the first counting cycle in the prior scanning sequence.

Claim 17

A scanner circuit comprising: counter circuit means for receiving counting pulses to provide sequential scanning pulses; circuit means for stopping said counter circuit in response to a signal condition caused by any of the scanner pulses, and control circuit means responsive to input signals for enabling said counter to start a preset number of successive counting cycles in a scanning sequence wherein the first counting cycle of a scanning sequence starts at the count at the end of the first counting cycle in the prior scanning sequence.

Claim 18

A scanner circuit as defined in claim 13 wherein said counter circuit means includes: circuit means for determining when a preset count is reached a first time in a scanning sequence for resetting the counter circuit means and for inhibiting said counter circuit means when the preset count is reached a second time until subsequently enabled by said control circuit means.

Claim 19

A scanner circuit as defined in claim 13 wherein said counter circuit means includes: circuit means for determining when a preset count is reached in a preset number of consecutive counting cycles in a scanning sequence for resetting the counter circuit means in each counting cycle and for inhibiting said counter circuit means when the preset count is reached an additional time until subsequently enabled by said control circuit means.