US3718904A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Nand gate realization of the n-input parity function
Assignee: AT&T Inc
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Filing: 1971-09-01
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Granted: 1973-02-27
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Expires: 1991-09-01
Abstract
Abstract A GENERALIZED, RECURSIVE, DESIGN PROCEDURE IS TAUGHT FOR SYNTHESIZING A PARITY CHECKING CIRCUIT COMPRISED SOLELY OF NAND GATES AND HAVING ANY ARBITRARY, INTEGRAL NUMBER K, GREATER THAN THREE, OF PARALLEL, BINARY INPUTS. INCREASED OPERATING SPEED IS ACHIEVED BY INTERCONNECTING PLURAL LOGIC LEVELS TOGETHER THROUGH A LEVEL OF INTERACTIVE NAND GATE LOGIC TO REDUCE THE NUMBER OF LOGIC LEVELS WHICH ARE NORMALLY REQUIRED TO IMPLEMENT SUCH A CIRCUIT.
Inventors
- 👤 A Bulfer
- 👤 E Tammaru
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:15
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 0
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References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-27 | 1976-08-28 | 1977-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-27 | 1980-08-28 | 1981-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-27 | 1984-08-28 | 1985-02-27 | $7700.00 | Window Closed / Lapsed |