Variable speed plural motor control system with incremental speed synchronization

Claim 2

A variable speed motor control system for driving a first a-c motor energized from a first inverter which receives timing pulses from a master source, including a system speed control unit connected to regulate the rate at which the timing pulses issue from the master source, a second a-c motor energized from a second inverter which receives timing pulses from a slave source, and the improvement which comprises a phaselock and position control subsystem, including: means for applying a signal from the system speed control unit to the slave source of timing pulses, a phase detector, connected to receive a first series of position-indicating signals which varies as a function of movement of the first a-c motor and to provide a first reset signal upon receipt of each position-indicating signal in the first series, and also connected to receive a second series of position-indicating signals which varies as a function of movement of the second a-c motor and to provide a second reset signal upon receipt of each position-indicating signal in the second series, a first register-and-dac, connected to receive an input signal from the master source and to provide a first ramp signal with a slope of given polarity, and also coupled to said phase detector so that the reset portion of the first ramp signal is determined by said first reseT signal, a second register-and-dac, connected to receive an input signal from the slave source and to provide a second ramp signal with a slope having a polarity opposite that of the first ramp signal and displaced in phase relative to the first ramp signal, and also coupled to said phase detector so that the reset portion of the second ramp signal is determined by said second reset signal, summing means for combining the ramp signals to provide a d-c control signal at a summation point, and means for applying the d-c control signal to the slave source of timing pulses, to maintain synchronized operation between the first and second a-c motors.

Claim 3

A variable speed motor control system as claimed in claim 1, in which the subsystem further comprises a position control unit, coupled to the summing means, such that adjustment of the position control unit modifies the d-c control signal and produces an incremental position displacement of the second a-c motor with respect to the first a-c motor, without disturbing the synchronized operation between the two motors.

Claim 4

A variable speed motor control system as claimed in claim 1, in which the summing means comprises first and second summing amplifiers respectively coupled to the dacs, and a pair of mixing resistors, each coupled between the summation point and one of the summing amplifiers, such that the d-c control signal is provided at the summation point for application to the slave source of timing pulses.

Claim 5

A variable speed motor control system as claimed in claim 1, in which the subsystem further comprises an out-of-sync circuit connected to receive both a first signal from the phase detector indicating in-phase and out-of-phase operation, and a second signal from the phase detector indicating under-speed and over-speed conditions when the system is out-of-phase, and means coupled between the out-of-sync circuit and the summing means, to override the d-c control signal when the system is out of phase and pass to the slave source a modified d-c signal to drive the system toward in-phase operation.

Claim 6

A variable speed motor control system as claimed in claim 1, in which the subsystem further comprises an amplifier-and-filter circuit, coupled between the summing means and the slave source of timing pulses, including means for adjusting the gain of the system and thus ad-justing variations in the duty cycle of the phase detector to maintain system accuracy.

Claim 7

A variable speed motor control system for driving a master a-c motor energized from a master inverter which receives timing pulses from a master vco, including a system speed control unit connected to regulate the rate at which the timing pulses issue from the master vco, and a slave a-c motor energized from a slave inverter which receives timing pulses from a slave vco, characterized by a phaselock and position control subsystem which includes: means for applying a signal from the system speed control unit to the slave vco, a phase detector, connected to receive a first series of low frequency position indicating signals which varies as a function of movement of the master a-c motor and to provide a first reset signal upon receipt of each position indicating signal in the first series, also connected to receive a second series of low frequency position indicating signals which varies as a function of movement of the slave a-c motor and to provide a second reset signal upon receipt of each position indicating signal in the second series, and also connected to provide a square wave output signal in which the positive-going and negative-going portions are determined by the first and second series of low frequency position indicating signals, a count-up register-and-dac, connected to receive a high frequency input signal from the master vco and to provide a first ramp signal with a positive slope, and also coupled to the phase detector so that the reset portion of the first ramp signal is determined by receipt of said first reset signal, a count-down register-and-dac, connected to receive a high frequency input signal from the slave vco and to provide a second ramp signal with a negative slope, which second ramp signal is displaced in phase with respect to the first ramp signal, and also coupled to the phase detector so that the reset portion of the second ramp signal is determined by receipt of said second reset signal, summing means for combining the positive-slope and negative which the timing pulses issue from the master vco, and a slave a-c motor energized from a slave inverter which receives timing pulses from a slave vco, characterized by a phaselock and position control subsystem which includes: means for applying a signal from the system speed control unit to the slave vco, a phase detector, connected to receive a first series of low frequency position indicating signals which varies as a function of movement of the master a-c motor and to provide a first reset signal upon receipt of each position indicating signal in the first series, also connected to receive a second series of low frequency position indicating signals which varies as a function of movement of the slave a-c motor and to provide a second reset signal upon receipt of each position indicating signal in the second series, and also connected to provide a square wave output signal in which the positive-going and negative-going portions are determined by the first and second series of low frequency position indicating signals, a count-up register-and-dac, connected to receive a high frequency input signal from the master vco and to provide a first ramp signal with a positive slope, and also coupled to the phase detector so that the reset portion of the first ramp sig-nal is determined by receipt of said first reset signal, a count-down register-and-dac, connected to receive a high frequency input signal from the slave vco and to provide a second ramp signal with a negative slope, which second ramp signal is displaced in phase with respect to the first ramp signal, and also coupled to the phase detector so that the reset portion of the second ramp signal is determined by receipt of said second reset signal, summing means for combining the positive-slope and negative-slope ramp signals with the phase detector square wave output signal to provide a d-c control signal at a summation point, and means for applying the d-c control signal to the slave vco, to maintain synchronized operation between the master and slave a-c motors.

Claim 8

A variable speed motor control system for driving a master a-c motor energized from a master inverter which receives timing pulses from a master vco, including a system speed control unit connected to regulate the rate at which the timing pulses issue from the master vco, and a slave a-c motor energized from a slave inverter which receives timing pulses from a slave vco, characterized by a phaselock and position control subsystem which includes: means for applying a signal from the system speed control unit to the slave vco, a phase detector, connected to receive a first series of low frequency position indicating signals which varies as a function of movement of the master a-c motor and to provide a first reset signal upon receipt of each position indicating signal in the first series, also connected to receive a second series of low frequency position indicating signals which varies as a function of movement of the slave a-c motor and to provide a second reset signal upon receipt of each position indicating signal in the second series, and also connected to provide a square wave output signal in which the positive-going and negative-going portions are determined by the first and second series of low frequency position indicating signals, a count-up register-and-dac, connected to receive a high frequency input signal from the master vco and to provide a first ramp signal with a positive slope, and also coupled to the phase detector so that the reset portion of the first ramp signal is determined by receipt of said first reset signal, a count-down register-and-dac, connected to receive a high frequency input signal from the slave vco and to provide a second ramp signal with a negative slope, which second ramp signal is displaced in phase with respect to the first ramp signal, and also coupled to the phase detector so that the reset portion of the second ramp signal is determined by receipt of said second reset signal, summing means for combining the positive-slope and negative which the timing pulses issue from the master vco, and a slave a-c motor energized from a slave inverter which receives timing pulses from a slave vco, characterized by a phaselock and position control subsystem which includes: means for applying a signal from the system speed control unit to the slave vco, a phase detector, connected to receive a first series of low frequency position indicating signals which varies as a function of movement of the master a-c motor and to provide a first reset signal upon receipt of each position indicating signal in the first series, also connected to receive a second series of low frequency position indicating signals which varies as a function of movement of the slave a-c motor and to provide a second reset signal upon receipt of each position indicating signal in the second series, and also connected to provide a square wave output signal in which the positive-going and negative-going portions are determined by the first and second series of low frequency position indicating signals, a count-up register-and-dac, connected to receive a high frequency input signal from the master vco and to provide a first ramp signal with a positive slope, and also coupled to the phase detector so that the reset portion of the first ramp sig-nal is determined by receipt of said first reset signal, a count-down register-and-dac, connected to receive a high frequency input signal from the slave vco and to provide a second ramp signal with a negative slope, which second ramp signal is displaced in phase with respect to the first ramp signal, and also coupled to the phase detector so that the reset portion of the second ramp signal is determined by receipt of said second reset signal, summing means for combining the positive-slope and negative-slope ramp signals with the phase detector square wave output signal to provide a d-c control signal at a summation point, and means for applying the d-c control signal to the slave vco, to maintain synchronized operation between the master and slave a-c motors.

Claim 9

A variable speed motor control system as claimed in claim 6, in which the subsystem further comprises a position control unit with a voltage-adjusting portion coupled to the summing means, such that movement of the voltage-adjusting portion modifies the d-c control signal at the summation point so that a modified d-c signal is applied to the slave vco, thus producing an incremental position displacement of the slave motor relative to the master motor without changing the synchronized operation of the two motors.

Claim 10

A variable speed motor control system as claimed in claim 6, in which the summing means includes first and second summing amplifiers individually coupled to the dacs, and a pair of mixing resistors of given value, each resistor coupled between the summation point and one of the summing amplifiers, such that the d-c control signal is provided at the summation point by combining the output signals from the summing amplifiers over the mixing resistors.

Claim 11

A variable speed motor control system as claimed in claim 8, in which the subsystem further comprises an out-of-sync circuit, a third resistor coupled between the out-of-sync circuit and the summation point, which third resistor has a value approximately an order of magnitude less than said given value, so that application of an override signal from the out-of-sync circuit swamps the d-c control signal at the summation point, thus driving the slave vco in the proper direction to achieve synchronized operation.

Claim 12

A variable speed motor control system as claimed in claim 9, in which the out-of-sync circuit is connected to receive a first input signal from the phase detector connoting in-phase and out-of-phase operation, and is also connected to receive a second input signal from the phase detector connoting underspeed and overspeed conditions.

Claim 13

A variable speed motor control system as claimed in claim 6, in which the means for applying the d-c control signal to the slave vco includes an amplifier-and-filter circuit having at least one amplifier stage, and having a variable resistor connected to adjust the system gain.

Claim 14

A variable speed motor control system as claimed in claim 11, in which the variable resistor is coupled in series with the main signal path through amplifier-and-filter circuit to adjust the system gain.

Claim 15

A variable speed motor control system for driving a first a-c motor energized from a first inverter which receives timing pulses from a master source, including a system speed control unit connected to regulate the rate at which the timing pulses issue from the master source, a second a-c motor energized from a second inverter which receives timing pulses from a slave source, and the improvement which comprises a phaselock and position control subsystem including: means for applying a signal from the system speed control unit to the slave source of timing pulses, a phase detector, connected to receive a first series of position-indicating signals which varies as a function of move-ment of the first a-c motor and to provide a first reset signal upon receipt of each position-indicating signal in the first series, also connected to receive a second series of position-indicating signals which varies as a function of movement of the second a-c motor and to provide a second reset signal upon receipt of each position-indicating signal in the second series, and to provide a square wave output signal in which the positive-going and negative-going portions are determined by the first and second series of position-indicating signals; a first function generator, connected to receive an input signal from the master source and to provide a first a-c signal with different parameters, in which one parameter is determined by receipt of said first reset signal from the phase detector, a second function generator, connected to receive an input signal from the slave source and to provide a second a-c signal with different parameters, one parameter having a polarity opposite that of the corresponding parameter in the first a-c signal and displaced in phase relative to the first a-c signal, in which another parameter of the second ramp signal is deter-mined by receipt of said second reset signal from the phase detector, summing means for combining the a-c signals with the square wave output signal of the phase detector to provide a d-c control signal at a summation point, which d-c control signal has virtually zero ripple voltage at the low-frequency rate of the position-indicating signals, and means for applying the d-c control signal to the slave source of timing pulses, to maintain synchronized operation between the first and second a-c motors.

Claim 16

A variable speed motor control system for driving a first a-c motor energized from a first inverter which receives timing pulses from a master source, including a system speed control unit connected to regulate the rate at which the timing pulses issue from the master source, a second a-c motor energized from a second inverter which receives timing pulses from a slave source, and the improvement which comprises a phaselock and position control subsystem including: means for applying a signal from the system speed control unit to the slave source of timing pulses, a phase detector, connected to receive a first series of position-indicating signals which varies as a function of move-ment of the first a-c motor and to provide a first reset signal upon receipt of each position-indicating signal in the first series, also connected to receive a second series of position-indicating signals which varies as a function of movement of the second a-c motor and to provide a second reset signal upon receipt of each position-indicating signal in the second series, and to provide a square wave output signal in which the positive-going and negative-going portions are determined by the first and second series of position-indicating signals; a first function generator, connected to receive an input signal from the master source and to provide a first a-c signal with different parameters, in which one parameter is determined by receipt of said first reset signal from the phase detector, a second function generator, connected to receive an input signal from the slave source and to provide a second a-c signal with different parameters, one parameter having a polarity opposite that of the corresponding parameter in the first a-c signal and displaced in phase relative to the first a-c signal, in which another parameter of the second ramp signal is deter-mined by receipt of said second reset signal from the phase detector, summing means for combining the a-c signals with the square wave output signal of the phase detector to provide a d-c control signal at a summation point, which d-c control signal has virtually zero ripple voltage at the low-frequency rate of the position-indicating signals, and means for applying the d-c control signal to the slave source of timing pulses, to maintain synchronized operation between the first and second a-c motors.