Address responsive controller for computer handling of peripheral equipment

Claim 2

In a system wherein a computer communicates with a number of peripheral devices, the improvement comprising: a plurality of controller circuits, a separate plurality of peripheral devices assigned to each controller circuit, means coupling all of said controller circuits to said computer, means coupling each separate plurality of peripheral devices to its assigned controller circuit, first address logic means in each controller for enabling a controller to become operative in response to a unique controller address signal, second address logic means at each peripheral device for enabling it to become operative in response to a unique peripheral device address signal, means for transmitting digital signals and first and second address signals from said computer to said controllers, means in a controller rendered operative responsive to its unique first address signal to store and process said second address and digital signals, means to transmit to all of its associated peripheral devices said stored and processed second address and said digital signals, and means in a peripheral device rendered operative responsive to its unique second address signal to respond to said digital signals.

Claim 3

In a system wherein a computer communicates with a number of peripheral devices, the improvement comprising: a plurality of controller circuits, a separate plurality of peripheral devices assigned to each controller circuit, means coupling all of said controller circuits to said computer, means coupling each separate plurality of peripheral devices to its assigned controller circuit, first address logic means in each controller for enabling a controller to become operative in response to a unique controller address signal, second address logic means at each peripheral device for enabling it to become operative in response to a unique peripheral device address signal, means for transmitting digital signals and first and second address signals from said computer to said controllers, means in a controller rendered operative responsive to its unique first address signal to store and process said second address and digital signals, means to transmit to all of its associated peripheral devices said stored and processed second address and said digital signals, and means in a peripheral device rendered operative responsive to its unique second address signal to respond to said digital signals.

Claim 4

In a system wherein a computer communicates with a number of peripheral devices, the improvement comprising: a plurality of controller circuits, a separate plurality of peripheral devices assigned to each controller circuit, means coupling all of said controller circuits to said computer, means coupling each separate plurality of peripheral devices to its assigned controller circuit, first address logic means in each controller for enabling a controller to become operative in response to a unique controller address signal, second address logic means at each peripheral device for enabling it to become operative in response to a unique peripheral device address signal, means for transmitting digital signals and first and second address signals from said computer to said controllers, means in a controller rendered operative responsive to its unique first address signal to store and process said second address and digital signals, means to transmit to all of its associated peripheral devices said stored and processed second address and said digital signals, and means in a peripheral device rendered operative responsive to its unique second address signal to respond to said digital signals.

Claim 5

In a system as recited in claim 1 wherein said means in a controller rendered operative responsive to its unique first address signal to store and process said second address and digital signals includes means responsive to signals from said computer for generating mode signals indicative of the nature of said digital signals, means in an operative controller for transmitting said mode signals to all of the peripheral devices associated therewith, and means in an operative peripheral device for utilizing said mode signals for decoding said digital signals.

Claim 6

In a system as recited in claim 2 wherein said mode signals represent that said digital signals are representative of a command, said controller includes means for converting said digital signals into command signals for said operative peripheral device, and means for transmitting said command signals to said peripheral devices in place of said digital signals.

Claim 7

In a system as recited in claim 2 wherein said mode signals represent that said digital signals are inquiring as to the status of an addressed operative peripheral device, said addressed operative peripheral device includes means responsive to said mode and digital signals for transmitting to said operative control device signals representative of the status of said addressed operative peripheral device, and said operative control device includes means for transmitting said signals representative of the status of said peripheral device to said computer.

Claim 8

In a system as recited in claim 2 wherein said mode signals represent that said digital signals represent a request for data from an addressed operative peripheral device, said addressed operative peripheral device includes means responsive to said mode and digital signals for transmitting requested data to said operative control device, and said operative control device includes means for transmitting said requested data to said computer.

Claim 9

In a system wherein a computer communicates with a number of peripheral devices, the improvement comprising: a plurality of controller circuits, a separate plurality of peripheral devices assigned to each controller circuit, means coupling all of said controller circuits to said computer, means coupling each separate plurality of peripheral devices to its assigned controller circuit, first address logic means in each controller for enabling a controller to become operative in response to a unique controller address signal, second unique address logic means at each peripheral device for enabling it to become operative in response to a unique peripheral device address signal, means for transmitting data and first and second address signals from said computer to said controllers, means at each controller for storing said data and said second address signals responsive to a controller being rendered operative in response to said first address signals, means for applying said stored data and said device address from the respective storage means to said means coupling said plurality of devices to its assigned controller, means at an operative controller for generating a timing signal, means for transmitting said timing signal to all of the peripheral devices assigned to said controller, means at an operative peripheral device for enabling decoding of said data signals responsive to a correct address and said timing signal, means for generating a second timing signal at an operative peripheral device responsive to a first timing signal and the decoding of said data signals, means for transmitting said second timing signal back to said controller associated with said peripheral device, and means at said controller for deenergizing said controller responsive to said second timing signal.

Claim 10

In a system wherein a computer communicates with a number of peripheral devices, the improvement comprising: a plurality of controller circuits, a separate plurality of peripheral devices assigned to each controller circuit, means coupling all of said controller circuits to said computer, means coupling each separate plurality of peripheral devices to its assigned controller circuit, first address logic means in each controller for enabling a controller to become operative in response to a unique controller address signal, second unique address logic means at each peripheral device for enabling it to become operative in response to a unique peripheral device address signal, means for transmitting data and first and second address signals from said computer to said controllers, means at each controller for storing said data and said second address signals responsive to a controller being rendered operative in response to said first address signals, means for applying said stored data and said device address from the respective storage means to said means coupling said plurality of devices to its assigned controller, means at an operative controller for generating a timing signal, means for transmitting said timing signal to all of the peripheral devices assigned to said controller, means at an operative peripheral device for enabling decoding of said data signals responsive to a correct address and said timing signal, means for generating a second timing signal at an operative peripheral device responsive to a first timing signal and the decoding of said data signals, means for transmitting said second timing signal back to said controller associated with said peripheral device, and means at said controller for deenergizing said controller responsive to said second timing signal.

Claim 11

Apparatus as recited in claim 6, wherein each controller includes means for generating mode signals indicative of the nature of the data signals stored in said data storage, and means for transmitting said mode signals to said energized peripheral device for use in decoding said data signals.

Claim 12

Apparatus as recited in claim 6 wherein there is included a busy flip-flop means responsive to the energization of said controller for providing a busy signal to said computer, and means for applying said second timing signal to said busy flip-flop means to reset it.