US3715574A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interface converter for feeding high frequency signals into low frequency circuits
Assignee: United States Department of the Navy
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Filing: 1971-07-21
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Granted: 1973-02-06
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Expires: 1991-07-21
Abstract
Abstract Apparatus for conversion of high speed binary to binary coded decimal with low speed circuitry. An information incoming pulse is digitized at the high frequency rate and this digital equivalent is stored in a first bit register. A low frequency digitizing oscillator is coupled through a gate circuit to a bit register identical to the first bit register and into a binaryto-digital converter. A bit by bit comparator compares the high frequency pulse count with the low frequency pulse count and produces a stop signal to the gate circuit when the low frequency count equals the stored high frequency count.
Inventors
- 👤 R Gowan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:46
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/02; H03M7/12
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
260 words
In an interface converting means for generating a low speed digitized signal that is the equivalent to the same information digitized at a high speed, the combination comprising: a. an input terminal for receiving a gate pulse to be digitized; b. a gated high frequency oscillator coupled to said input terminal and being gated on for the duration of said gate pulse to be digitized, c. a low frequency oscillator, d. a first counting and storage bit register coupled to said gated high frequency oscillator for counting and storing the number of pulses received during said gate pulse duration, e. a gate circuit having a first input coupled to said low frequency oscillator, a second input, a third input and an output, f. a ready bit circuit connected in circuit with the second input of said gate circuit and said input terminal and being responsive to the termination of said gate pulse duration to turn on said gate circuit allowing low frequency pulses to flow through, g. a second counting and storage bit register coupled to the output of said gate circuit for counting and storing low frequency pulses flowing through said gate circuit, h. comparator circuit means coupled to said first and second counting and storage bit register and having an output coupled to the third input of said gate circuit for gating off said gate circuit when the number of low frequency pulses received in said second counting and storage bit register equal the number of high frequency pulses stored in said first counting and storage bit register.
Claim 2
Dependent Claim
260 words
In an interface converting means for generating a low speed digitized signal that is the equivalent to the same information digitized at a high speed, the combination comprising: a. an input terminal for receiving a gate pulse to be digitized; b. a gated high frequency oscillator coupled to said input terminal and being gated on for the duration of said gate pulse to be digitized, c. a low frequency oscillator, d. a first counting and storage bit register coupled to said gated high frequency oscillator for counting and storing the number of pulses received during said gate pulse duration, e. a gate circuit having a first input coupled to said low frequency oscillator, a second input, a third input and an output, f. a ready bit circuit connected in circuit with the second input of said gate circuit and said input terminal and being responsive to the termination of said gate pulse duration to turn on said gate circuit allowing low frequency pulses to flow through, g. a second counting and storage bit register coupled to the output of said gate circuit for counting and storing low frequency pulses flowing through said gate circuit, h. comparator circuit means coupled to said first and second counting and storage bit register and having an output coupled to the third input of said gate circuit for gating off said gate circuit when the number of low frequency pulses received in said second counting and storage bit register equal the number of high frequency pulses stored in said first counting and storage bit register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-06 | 1976-08-07 | 1977-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-06 | 1980-08-07 | 1981-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-06 | 1984-08-07 | 1985-02-06 | $7700.00 | Window Closed / Lapsed |