Digital signal processor for use in a hyperbolic radio navigation receiver

Claim 2

In a hyperbolic navigation receiver a digital signal processor comprising first limiter means for amplitude limiting signals received by said receiver, gating means coupled to said limiter means for obtaining a plurality of samples from said limited received signals, first integrator means responsive to said plurality of samples and compressing said plurality of samples into multi-level pulses, second limiter means coupled to said first integrator means for comparing said multi-level pulses with a reference level to produce difference signal outputs, and second integrator means for receiving and integrating said difference signal outputs to provide integrated output data which is indicative of the navigation information contained in said received signal.

Claim 3

In a hyperbolic navigation receiver a digital signal processor comprising first limiter means for amplitude limiting signals received by said receiver, gating means coupled to said limiter means for obtaining a plurality of samples from said limited received signals, first integrator means responsive to said plurality of samples and compressing said plurality of samples into multi-level pulses, second limiter means coupled to said first integrator means for comparing said multi-level pulses with a reference level to produce difference signal outputs, and second integrator means for receiving and integrating said difference signal outputs to provide integrated output data which is indicative of the navigation information contained in said received signal.

Claim 4

In a hyperbolic navigation receiver a digital signal processor comprising first limiter means for amplitude limiting signals received by said receiver, gating means coupled to said limiter means for obtaining a plurality of samples from said limited received signals, first integrator means responsive to said plurality of samples and compressing said plurality of samples into multi-level pulses, second limiter means coupled to said first integrator means for comparing said multi-level pulses with a reference level to produce difference signal outputs, and second integrator means for receiving and integrating said difference signal outputs to provide integrated output data which is indicative of the navigation information contained in said received signal.

Claim 5

In a hyperbolic navigation receiver a digital signal processor comprising first limiter means for amplitude limiting signals received by said receiver, gating means including trigger pulses positionable in time coupled to said limiting means for obtaining a plurality of samples from said limited received signals only during the occurrence of said trigger pulses, first integrator means responsive to said plurality of samples and compressing said plurality of samples into multi-level pulses, second limiter means coupled to said first integrator means for comparing said multi-level pulses with a reference level to produce difference signal outputs, second integrator means for receiving said difference signal outputs and providing integrated data outputs, control means responsive to said integrated data outputs for providing time displacement of said positionable trigger pulses prior to sampling said limited received signals, and display means responsive to said integrated data output for providing a visual readout of the navigation information contained in said received signals.

Claim 6

In a hyperbolic navigation receiver a digital signal processor comprising first limiter means for amplitude limiting signals received by said receiver, gating means including trigger pulses positionable in time coupled to said limiting means for obtaining a plurality of samples from said limited received signals only during the occurrence of said trigger pulses, first integrator means responsive to said plurality of samples and compressing said plurality of samples into multi-level pulses, second limiter means coupled to said first integrator means for comparing said multi-level pulses with a reference level to produce difference signal outputs, second integrator means for receiving said difference signal outputs and providing integrated data outputs, control means responsive to said integrated data outputs for providing time displacement of said positionable trigger pulses prior to sampling said limited received signals, and display means responsive to said integrated data output for providing a visual readout of the navigation information contained in said received signals.

Claim 7

In a hyperbolic navigation receiver a digital signal processor comprising first limiter means for amplitude limiting signals received by said receiver, gating means coupled to said limiter means for obtaining a plurality of polarity samples from said limited received signals, first integrator means responsive to said plurality of polarity samples and compressing said samples into multi-level pulses, second limiter means coupled to said first integrator means for comparing said multi-level pulses with a reference level to produce polarized difference signals and second integrator means for receiving and integrating said polarized difference signals to provide integrated output data which is indicative of the navigation information contained in said received signals.

Claim 8

In a hyperbolic navigation receiver a digital signal processor comprising first limiter means for amplitude limiting signals received by said receiver, gating means coupled to said limiter means for obtaining a plurality of polarity samples from said limited received signals, first integrator means responsive to said plurality of polarity samples and compressing said samples into multi-level pulses, second limiter means coupled to said first integrator means for comparing said multi-level pulses with a reference level to produce polarized difference signals and second integrator means for receiving and integrating said polarized difference signals to provide integrated output data which is indicative of the navigation information contained in said received signals.

Claim 9

In a Loran tracking receiver for indicating the time difference between received Loran master and a plurality of Loran slave pulse groups a digital signal processor comprising first limiter means for converting said received Loran pulse groups to sqUare wave pulse groups, pulse sampling means connected to said first limiter means for sampling phases of particular cycles within each pulse of said square wave pulse groups producing sample signals representative of said sampled phases, first integrator means responsive to said sample signals and compressing said sample signals into multi-level pulses, second limiter means connected to said first integrator means which compares said multi-level pulses to a locally generated voltage level producing limited output signals, second integrator means coupled to said second limiter means and summing said limited output signals to produce integrator outputs indicative of said time difference between said received Loran pulse groups; and indicator means responsive to said integrator outputs for providing a visual display of said time difference between said received Loran pulse groups.

Claim 10

In a Loran tracking receiver for indicating the time difference between received Loran master and a plurality of Loran slave pulse groups a digital signal processor comprising first limiter means for converting said received Loran pulse groups to sqUare wave pulse groups, pulse sampling means connected to said first limiter means for sampling phases of particular cycles within each pulse of said square wave pulse groups producing sample signals representative of said sampled phases, first integrator means responsive to said sample signals and compressing said sample signals into multi-level pulses, second limiter means connected to said first integrator means which compares said multi-level pulses to a locally generated voltage level producing limited output signals, second integrator means coupled to said second limiter means and summing said limited output signals to produce integrator outputs indicative of said time difference between said received Loran pulse groups; and indicator means responsive to said integrator outputs for providing a visual display of said time difference between said received Loran pulse groups.

Claim 11

In a Loran tracking receiver for indicating the time difference between received Loran master and a plurality of Loran slave pulse groups a digital signal processor comprising first limiter means for converting said received Loran pulse groups to square wave pulse groups, envelope deriver means for obtaining derived pulse groups from said received Loran pulse groups, second limiter means for converting said derived pulse groups to square wave derived pulse groups, pulse sampling means connected to said first and second limiter means for sampling phases of particular cycles within each pulse of said square wave pulse groups and square wave derived pulse groups producing sample signals representative of said sampled phases, first integrator means responsive to said sample signals and compressing said sample signals into multi-level pulses, third limiter means connected to said first integrator means which compares said multi-level pulses to a locally generated voltage level producing limited output signals, second integrator means coupled to said third limiter means and summing said limited output signals to produce integrator outputs indicative of said time difference between received Loran pulse groups and indicator means responsive to said integrator outputs for indicating the time difference between said received Loran pulse groups.

Claim 12

In a Loran tracking receiver for indicating the time difference between received Loran master and a plurality of Loran slave pulse groups a digital signal processor comprising first limiter means for converting said received Loran pulse groups to square wave pulse groups, envelope deriver means for obtaining derived pulse groups from said received Loran pulse groups, second limiter means for converting said derived pulse groups to square wave derived pulse groups, pulse sampling means connected to said first and second limiter means for sampling phases of particular cycles within each pulse of said square wave pulse groups and square wave derived pulse groups producing sample signals representative of said sampled phases, first integrator means responsive to said sample signals and compressing said sample signals into multi-level pulses, third limiter means connected to said first integrator means which compares said multi-level pulses to a locally generated voltage level producing limited output signals, second integrator means coupled to said third limiter means and summing said limited output signals to produce integrator outputs indicative of said time difference between received Loran pulse groups and indicator means responsive to said integrator outputs for indicating the time difference between said received Loran pulse groups.

Claim 13

In a Loran tracking receiver as described in claim 5 in which said pulse sampling means includes integrated pulse sampling circuits which conduct only during the occurrence of positionable trigger pulses, and control means responsive to said integrator outputs for providing time displacement of said positionable trigger pulses prior to sampling said phases of particular cycles.

Claim 14

In a Loran tracking receiver as described in claim 5 in which said first integrator means includes a tapped shift register and a summation network.

Claim 15

In a Loran tracking receiver as described in claim 7 in which said summation network includes a resistive matrix.

Claim 16

In a Loran tracking receiver as described in claim 5 in which said second integrator means includes the parallel combination of electronic integrators and servo motors.