US3714634A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and system for sorting without comparator
Assignee: Dirks Electronics Corp
•
Filing: 1971-01-07
•
Granted: 1973-01-30
•
Expires: 1991-01-07
Abstract
Abstract Record unit addresses, providing access to corresponding record units having keyfields, are stored in a first storage, each under control of the corresponding least significant keyfield bit. Zero keyfield bits cause storage of record unit addresses in sequential locations following a ''''0'''' assigned storage location; ''''1'''' keyfield bits cause storage of record unit addresses in sequential locations following a ''''1'''' assigned storage location. Record unit addresses in the ''''0'''' assigned storage locations of the first storage are then transferred to a second storage in the same manner under control of the next significant keyfield bit. Next, the record unit addresses in the ''''1'''' assigned storage locations of the first storage are so transferred to the second storage. The transfers are repeated under control of all keyfield bits, read-out from ''''0'''' assigned storage locations always preceding read-out from ''''1'''' assigned storage locations.
Inventors
- 👤 G Dirks
- 👤 P Schenck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:51
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/22; G06F7/24; G06F2207/00; G06F2207/22; G06F2207/222; Y; Y10; Y10S; Y10S707/00; Y10S707/99931; Y10S707/99937
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
261 words
In a data handling system handling record units each having a keyfield, each of said keyfields comprising a plurality of keyfield bits arranged in a predetermined order of place value, a system for arranging said record units in accordance with the values of said keyfields, comprising, in combination, register means, storing said keyfield bits in addressable register locations; first and second record unit address storage means each having a ''''0'''' assigned storage location and a ''''1'''' assigned storage location; input means operatively associated with said first record unit storage means for entering record unit addresses, each providing access to a corresponding record unit, into said first record unit address storage means; register addressing means connected to said register means and said first and second register unit address storage means and furnishing selectEd keyfield bits at least in part under control of said record unit addresses; and address transfer means interconnecting said first and second record unit address storage means and said register means, for transferring record unit addresses back and forth between said first and second record unit storage means at least in part under control of said selected keyfield bits, in such a manner that all record unit addresses under control of ''''0'''' selected keyfield bits are transferred to consecutively addressable record unit address storage locations starting with said ''''0'''' assigned record unit address storage location and all record unit addresses under control of a ''''1'''' selected key field bit are transferred into consecutively addressable record unit address storage locations starting with said ''''1'''' assigned record unit address storage location.
Claim 2
Dependent Claim
261 words
In a data handling system handling record units each having a keyfield, each of said keyfields comprising a plurality of keyfield bits arranged in a predetermined order of place value, a system for arranging said record units in accordance with the values of said keyfields, comprising, in combination, register means, storing said keyfield bits in addressable register locations; first and second record unit address storage means each having a ''''0'''' assigned storage location and a ''''1'''' assigned storage location; input means operatively associated with said first record unit storage means for entering record unit addresses, each providing access to a corresponding record unit, into said first record unit address storage means; register addressing means connected to said register means and said first and second register unit address storage means and furnishing selectEd keyfield bits at least in part under control of said record unit addresses; and address transfer means interconnecting said first and second record unit address storage means and said register means, for transferring record unit addresses back and forth between said first and second record unit storage means at least in part under control of said selected keyfield bits, in such a manner that all record unit addresses under control of ''''0'''' selected keyfield bits are transferred to consecutively addressable record unit address storage locations starting with said ''''0'''' assigned record unit address storage location and all record unit addresses under control of a ''''1'''' selected key field bit are transferred into consecutively addressable record unit address storage locations starting with said ''''1'''' assigned record unit address storage location.
Claim 3
Dependent Claim
261 words
In a data handling system handling record units each having a keyfield, each of said keyfields comprising a plurality of keyfield bits arranged in a predetermined order of place value, a system for arranging said record units in accordance with the values of said keyfields, comprising, in combination, register means, storing said keyfield bits in addressable register locations; first and second record unit address storage means each having a ''''0'''' assigned storage location and a ''''1'''' assigned storage location; input means operatively associated with said first record unit storage means for entering record unit addresses, each providing access to a corresponding record unit, into said first record unit address storage means; register addressing means connected to said register means and said first and second register unit address storage means and furnishing selectEd keyfield bits at least in part under control of said record unit addresses; and address transfer means interconnecting said first and second record unit address storage means and said register means, for transferring record unit addresses back and forth between said first and second record unit storage means at least in part under control of said selected keyfield bits, in such a manner that all record unit addresses under control of ''''0'''' selected keyfield bits are transferred to consecutively addressable record unit address storage locations starting with said ''''0'''' assigned record unit address storage location and all record unit addresses under control of a ''''1'''' selected key field bit are transferred into consecutively addressable record unit address storage locations starting with said ''''1'''' assigned record unit address storage location.
Claim 4
Dependent Claim
261 words
In a data handling system handling record units each having a keyfield, each of said keyfields comprising a plurality of keyfield bits arranged in a predetermined order of place value, a system for arranging said record units in accordance with the values of said keyfields, comprising, in combination, register means, storing said keyfield bits in addressable register locations; first and second record unit address storage means each having a ''''0'''' assigned storage location and a ''''1'''' assigned storage location; input means operatively associated with said first record unit storage means for entering record unit addresses, each providing access to a corresponding record unit, into said first record unit address storage means; register addressing means connected to said register means and said first and second register unit address storage means and furnishing selectEd keyfield bits at least in part under control of said record unit addresses; and address transfer means interconnecting said first and second record unit address storage means and said register means, for transferring record unit addresses back and forth between said first and second record unit storage means at least in part under control of said selected keyfield bits, in such a manner that all record unit addresses under control of ''''0'''' selected keyfield bits are transferred to consecutively addressable record unit address storage locations starting with said ''''0'''' assigned record unit address storage location and all record unit addresses under control of a ''''1'''' selected key field bit are transferred into consecutively addressable record unit address storage locations starting with said ''''1'''' assigned record unit address storage location.
Claim 5
Dependent Claim
46 words
A system as set forth in claim 1, further comprising register input means for entering into said register means, in sequence, a plurality of sets of key field bits, each set comprising a key field bit of predetermined place value from each of said record units.
Claim 6
Dependent Claim
24 words
A system as set forth in claim 2, wherein said predetermined place value is the same place value for each of said record units.
Claim 7
Dependent Claim
54 words
A system as set forth in claim 3, further comprising timing signal furnishing means furnishing bit time signals; and mode control means interconnected between said timing signal furnishing means and said address transfer means for initiating transfers between said first and second record unit address storage means in response to said bit time signals.
Claim 8
Dependent Claim
26 words
A system as set forth in claim 4, wherein said register input means furnish said sets of key field bits in ascending order of place value.
Claim 9
Dependent Claim
64 words
A system as set forth in claim 4, wherein said timing signal furnishing means also furnish a plurality of subbit time signals between consecutive ones of said bit time signals; wherein said input means comprise counter means furnishing counter output signals in response to said subbit time signals; and first gating means interconnecting said counter means and said first record unit address storage means.
Claim 10
Dependent Claim
16 words
A system as set forth in claim 4, wherein said register addressing means comprise multiplexer means.
Claim 11
Dependent Claim
53 words
A system as set forth in claim 4, wherein said mode control means comprise bistable circuit means furnishing a first and second mode control signal in a first and second stable state respectively, and changing from one of said stable states to the other in response to each of said bit time signals.
Claim 12
Dependent Claim
103 words
A system as set forth in claim 8, wherein said address transfer means comprise first output gating means having a first input connected to the output of said first record unit address storage means, a second input connected to said mode control means, and an output connected to the input of said second record unit address storage means; and second output gating means having a first input connected to the output of said second record unit address storage means, a second input connected to said mode control means, and an output connected to the input of said first record unit address storage means.
Claim 13
Dependent Claim
71 words
A system as set forth in claim 9, wherein said address transfer means further comprise first and second storage location selector means operatively associated with said first and second record unit address storage means respectively, each furnishing a selector output signal enabling a selected storage location in its associated record unit address storage means for read-out or recording, in response to a corresponding mode control signal and a selected keyfield bit.
Claim 14
Dependent Claim
68 words
A system as set forth in claim 10, wherein said first storage location selector means comprise ''''0'''' address counter means and ''''1'''' address counter means, respec-tively furnishing a ''''0'''' selector output signal for each record unit address transferRed under control of a ''''0'''' selected key field bit and a ''''1'''' selector output signal for each record unit address transferred under control of a ''''1'''' selected key field bit.
Claim 15
Dependent Claim
57 words
A system as set forth in claim 11, wherein said ''''0'''' address counter means has an enable input, a counting input and a reset input; further comprising ''''0'''' counter gating means furnishing an enable signal to said enable input in response to simultaneous occurrence of a ''''0'''' selected key field bit and said first mode control signal.
Claim 16
Dependent Claim
57 words
A system as set forth in claim 12, wherein said ''''1'''' address counter means has an enable input, a counting input, and a reset input; further comprising ''''1'''' counter gating means furnishing an enable signal to said enable input in response to simultaneous occurrence of a ''''1'''' selected key field bit and said first mode control signal.
Claim 17
Dependent Claim
25 words
A system as set forth in claim 13, wherein said ''''0'''' counter gating means and said ''''1'''' counter gating means each comprise an AND gate.
Claim 18
Dependent Claim
56 words
A system as set forth in claim 13, wherein said timing signal furnishing means further furnish a plurality of subbit time signals corresponding in number to said plurality of record unit addresses, between consecutive bit time signals; and means applying said subbit time signals to said counting inputs of said ''''0'''' and ''''1'''' address counter means.
Claim 19
Dependent Claim
66 words
A system as set forth in claim 15, wherein said first storage location selector means further comprise comparator means having a first and second comparator input respectively connected to the output of said ''''0'''' and said ''''1'''' address counter means, for furnishing a comparator output signal at a comparator output when said ''''0'''' selector output signal and said ''''1'''' selector output signal have a predetermined relationship.
Claim 20
Dependent Claim
43 words
A system as set forth in claim 16, wherein said first storage location selector means further comprise end load gating means for furnishing an ''''end load'''' signal in response to simultaneous presence of said first mode control signal and said comparator output signal.
Claim 21
Dependent Claim
25 words
A system as set forth in claim 17, further comprising means for furnishing a ''''read start'''' signal following in time upon said ''''end load'''' signal.
Claim 22
Dependent Claim
52 words
A system as set forth in claim 18, wherein said first storage location selector means further comprise ''''0'''' reset gating means responsive to the simultaneous presence of a said ''''read start'''' signal and said comparator output signal for furnishing a reset signal to said reset input of said ''''0'''' address counter means.
Claim 23
Dependent Claim
71 words
A system as set forth in claim 19, wherein said first storage location selector means further comprise first and second flip-flop means each having a set and reset output, a set and reset enable input, and a clock input, said second flip-flop means further having a clear direct input; means applying said ''''read start'''' signal to said clear direct input and to said set enable input of said first flip-flop means.
Claim 24
Dependent Claim
56 words
A system as set forth in claim 20, wherein said first storage location selector means further comprise additional ''''0'''' counter gating means furnishing an enable signal to said enable input of said ''''0'''' address counter means in response to simultaneous presence of said reset output of said second flip-flop means and said second mode control signal.
Claim 25
Dependent Claim
88 words
A system as set forth in claim 21, wherein said first storage selector means further comprise first and second flip-flops and AND gates, each having a first input connected to said set output of said first flip-flop means and a second input connected to the output of said comparator means, said first flip-flop AND gate having an output connected to said set enable input of said second flip-flOp means, said second flip-flop AND gate having an output connected to said reset enable input of said second flip-flop means.
Claim 26
Dependent Claim
58 words
A system as set forth in claim 22, wherein said first storage selector means further comprise ''''1'''' reset gating means responsive to simultaneous presence of said set output of said first flip-flop means, said comparator output signal, and said second mode control signal, and furnishing a reset signal to said reset input of said one address counter means.
Claim 27
Dependent Claim
57 words
A system as set forth in claim 23, wherein said first storage location selector means further comprise additional ''''1'''' counter gating means for furnishing an enable signal to said enable input of said ''''1'''' address counter means in response to simultaneous presence of said second mode control signal and said set output of said second flip-flop means.
Claim 28
Dependent Claim
61 words
A system as set forth in claim 13, wherein said first storage location selector means further comprise selection circuit means for selecting a ''''0'''' selector output signal to constitute said selector output signal upon occurrence of a ''''0'''' counter enable signal, and said ''''1'''' selector output signal to constitute said selector output signals upon occurrence of a ''''1'''' counter enable signal.
Claim 29
Dependent Claim
94 words
A system as set forth in claim 25, wherein said selector circuit means comprise second multiplexer means having a first input connected to the output of said ''''0'''' address counter means, a second input connected to the output of said ''''1'''' address counter means, a first and second selection input, and a second multiplexer output connected to said first record unit address storage means; and means interconnecting said first and second selection input of said second multiplexer means with the outputs of said ''''0'''' counter gating means and said ''''1'''' counter gating means, respectively.
Claim 30
Dependent Claim
76 words
A system as set forth in claim 1, further comprising first cyclic storage means storing said record units in an arbitrary sequence; read out means operatively associated with said first cyclic storage means; and register input means interconnecting said read out means and said register means for storing in said addressable register storage locations, in sequence, a plurality of sets of record unit bits, each set comprising a corresponding bit from each of said record units.
Claim 31
Dependent Claim
62 words
A system as set forth in claim 27, further comprising timing signal furnishing means furnishing bit time signals, and a plurality of subbit time signals corresponding in number to said plurality of record units between consecutive ones of said bit time signals; and wherein said register input means furnish said sets of record unit bits in synchronism with said bit time signals.
Claim 32
Dependent Claim
41 words
A system as set forth in claim 28, wherein said first cyclic storage means store said record units in an interlaced pattern; wherein said read-out means comprise a single read-out element; and wherein said register input means comprise serial-parallel converter means.
Claim 33
Dependent Claim
42 words
A system as set forth in claim 28, wherein said first cyclic storage means store said record units in a non-interlaced pattern; and wherein said read-out means comprise a plurality of read-out elements corresponding in number to said plurality of record units.
Claim 34
Dependent Claim
47 words
A system as set forth in claim 28, further comprising synchronizing means synchronizing said register input means to said first cyclic storage means in such a manner that said plurality of sets of keyfield bits precedes in time all others of said sets of record unit bits.
Claim 35
Dependent Claim
131 words
A system as set forth in claim 31 wherein said address transfer means comprise output gating means furnishing selected record unit addresses stored in one of said first and second record unit address storage means in synchronism with said subbit time signals; wherein said register addressing means, responsive to each of said selected record uNit addresses address the storage location in said register means corresponding to said selected record unit address, whereby said selected keyfield bit is the keyfield bit of the corresponding record unit; and wherein said address transfer means further comprise means for entering said record unit address into a ''''0'''' assigned storage location or a ''''1'''' assigned storage location in the other of said record unit storage means in dependence on the value of said selected keyfield bit.
Claim 36
Dependent Claim
117 words
A system as set forth in claim 32, wherein said first and second record unit address storage means are non-destructive read-out storage means; further comprising mode control means establishing the direction of transfer between said first and second record unit address storage means; third control means connected to the input of said mode control means for changing said direction of transfer in response to each bit time signal occurring during keyfield read-out time; cyclic output storage means; further comprising data transfer gating means interconnecting said register means and said cyclic output storage means upon receipt of data transfer gating signals; and means for furnishing said data transfer gating signals following in time upon said keyfield read-out time.
Claim 37
Dependent Claim
202 words
A computer method for sorting a plurality of record units each having a keyfield, in accordance with the code value of said keyfields, wherein each of said keyfields includes a plurality of keyfield bits arranged in a predetermined keyfield bit order, comprising, in combination, the steps of: generating a plurality of record unit address signals each accessing a corresponding one of said record units, to form a first address sequence; processing said first address sequence signals to form a first and second address sub-sequence comprising, respectively, all addresses accessing record units whose first keyfield bit in said predetermined keyfield bit order is ''''0'''' and ''''1''''; combining said first and second address sub-sequences into a second address sequence wherein the members of said first address subsequence precede the members of said second address subsequence; repeating said steps of processing and combining under control of all remaining keyfield bits to provide a final record unit address sequence; and selectively transferring said record units from a first to a second storage in a single pass in an access sequence controlled by said final address sequence, whereby said record units are stored in said second storage in an ordered sequence according to their relative keyfield values.
Claim 38
Dependent Claim
202 words
A computer method for sorting a plurality of record units each having a keyfield, in accordance with the code value of said keyfields, wherein each of said keyfields includes a plurality of keyfield bits arranged in a predetermined keyfield bit order, comprising, in combination, the steps of: generating a plurality of record unit address signals each accessing a corresponding one of said record units, to form a first address sequence; processing said first address sequence signals to form a first and second address sub-sequence comprising, respectively, all addresses accessing record units whose first keyfield bit in said predetermined keyfield bit order is ''''0'''' and ''''1''''; combining said first and second address sub-sequences into a second address sequence wherein the members of said first address subsequence precede the members of said second address subsequence; repeating said steps of processing and combining under control of all remaining keyfield bits to provide a final record unit address sequence; and selectively transferring said record units from a first to a second storage in a single pass in an access sequence controlled by said final address sequence, whereby said record units are stored in said second storage in an ordered sequence according to their relative keyfield values.
Claim 39
Dependent Claim
401 words
A computer method for sorting a plurality of record units each having a coded value keyfield, in order of relative keyfield value, comprising the steps of: a. storing said keyfield bits in a temporary storage having individually accessible storage locations each storing keyfield information relating to a corresponding one of said record units; b. generating a sequence of address signals to form a first address sequence, each of said address signals being associated with a corresponding one of said keyfield storage locations to provide access thereto, each of said address signals also accessing the record unit containing the keyfield information in the associated storage location; c. reading the first keyfield bit in said predetermined keyfield bit order of each of said record unit keyfields under sequence control of the associated elements of said first address sequence; d. processing the signals representing said first address sequence under transfer control of the values of said first keyfield bits to provide first and second address subsequences, comprising respectively all addresses accessing record units whose first keyfield bit is ''''0'''' and ''''1''''; e. combining said first and second address sub-sequences into a second address sequence, wherein the elements of said first address subsequence precede the elemeNts of said second address subsequence; f. reading the next successive keyfield bit of each of said record units under sequence control of the associated elements of said second address sequence; g. processing the signals representing said second address sequence under transfer control of the values of said next successive keyfield bits to provide third and fourth address subsequences, comprising respectively, all addresses accessing record units wherein said next successive keyfield bit is ''''0'''' and ''''1''''; h. combining said third and fourth address subsequences into a third address sequence wherein the elements of said third address subsequence precede the elements of said fourth address subsequence; i. repeating said steps of reading corresponding successive keyfield bits of each of said record units under sequence control of the previous address sequence, processing said previous address sequence under transfer control of said keyfield bit values to form two subsequences therefrom and combining said two subsequences to form a new address sequence, under control of all remaining keyfield bit positions until a final address sequence is obtained; and j. selectively transferring said record units in one pass from a first to a second storage in an access sequence controlled by said final address sequence.
Claim 40
Dependent Claim
401 words
A computer method for sorting a plurality of record units each having a coded value keyfield, in order of relative keyfield value, comprising the steps of: a. storing said keyfield bits in a temporary storage having individually accessible storage locations each storing keyfield information relating to a corresponding one of said record units; b. generating a sequence of address signals to form a first address sequence, each of said address signals being associated with a corresponding one of said keyfield storage locations to provide access thereto, each of said address signals also accessing the record unit containing the keyfield information in the associated storage location; c. reading the first keyfield bit in said predetermined keyfield bit order of each of said record unit keyfields under sequence control of the associated elements of said first address sequence; d. processing the signals representing said first address sequence under transfer control of the values of said first keyfield bits to provide first and second address subsequences, comprising respectively all addresses accessing record units whose first keyfield bit is ''''0'''' and ''''1''''; e. combining said first and second address sub-sequences into a second address sequence, wherein the elements of said first address subsequence precede the elemeNts of said second address subsequence; f. reading the next successive keyfield bit of each of said record units under sequence control of the associated elements of said second address sequence; g. processing the signals representing said second address sequence under transfer control of the values of said next successive keyfield bits to provide third and fourth address subsequences, comprising respectively, all addresses accessing record units wherein said next successive keyfield bit is ''''0'''' and ''''1''''; h. combining said third and fourth address subsequences into a third address sequence wherein the elements of said third address subsequence precede the elements of said fourth address subsequence; i. repeating said steps of reading corresponding successive keyfield bits of each of said record units under sequence control of the previous address sequence, processing said previous address sequence under transfer control of said keyfield bit values to form two subsequences therefrom and combining said two subsequences to form a new address sequence, under control of all remaining keyfield bit positions until a final address sequence is obtained; and j. selectively transferring said record units in one pass from a first to a second storage in an access sequence controlled by said final address sequence.
Claim 41
Independent Claim
470 words
A method for sorting a plurality of record units each having a keyfield in order of ascending keyfield value wherein each of said keyfields includes a plurality of keyfield bits arranged in a predetermined keyfield bit order to collectively form said value, comprising the steps of: a. storing the low order bit of each of said keyfields in selectively addressable storage locations within a holding register; b. generating a first sequence of address signals; c. associating each of said address signals with a corresponding one of said storage locations, said address signals accessing the entire record unit of which the keyfield bit in the associated storage location is a part; d. interrogating each of said low order keyfield bits in a sequence controlled by said first address sequence; e. processing said first address sequence signals under transfer control of said sequentially interrogated low order keyfield bits to provide a first address subsequence including all addresses accessing record units whose low order keyfield bit is ''''0'''' and a second address subsequence including all addresses accessing record units whose low order keyfield bit is ''''1''''; f. combining said first and second address subsequences to form a second address sequence, wherein the elements of said first address subsequence precede the elements of said second address subsequence; g. storing the next higher keyfield bit of each of said keyfields in the same holding register storage locations which held the low order keyfield bit of the same keyfield; h. interrogating each of said next higher keyfield bits in a sequence controlled by said second address sequence; i. processing said second address sequence under control of said sequentially interrogated next higher keyfield bits to provide a third address subsequence including all addresses accessing record units whose said next higher keyfield bit is a ''''0'''' and a fourth address subsequence including all addresses accessing record units whose said next higher keyfield bit is a ''''1''''; j. combining said third and fourth address subsequences to form a third address sequence wherein the elements of said third address subsequence precede the elements of said fourth address subsequence; k. repeating said steps of storing the next higher keyfield bits, interrogating them in a sequence controlled by the previously combined address sequence and processing said previously combined address sequence under transfer control of said sequentially interrogated keyfield bits to form two new address subsequences which are then Combined to form a new address sequence, until the high order keyfield bit of each of said record units has been interrogated and a final address sequence has been produced; l. selectively transferring said record units from a first random access storage to a second data storage in an access sequence controlled by said final address sequence, whereby said record units are stored on said second data storage in sequence of ascending keyfield value.
Claim 42
Independent Claim
470 words
A method for sorting a plurality of record units each having a keyfield in order of ascending keyfield value wherein each of said keyfields includes a plurality of keyfield bits arranged in a predetermined keyfield bit order to collectively form said value, comprising the steps of: a. storing the low order bit of each of said keyfields in selectively addressable storage locations within a holding register; b. generating a first sequence of address signals; c. associating each of said address signals with a corresponding one of said storage locations, said address signals accessing the entire record unit of which the keyfield bit in the associated storage location is a part; d. interrogating each of said low order keyfield bits in a sequence controlled by said first address sequence; e. processing said first address sequence signals under transfer control of said sequentially interrogated low order keyfield bits to provide a first address subsequence including all addresses accessing record units whose low order keyfield bit is ''''0'''' and a second address subsequence including all addresses accessing record units whose low order keyfield bit is ''''1''''; f. combining said first and second address subsequences to form a second address sequence, wherein the elements of said first address subsequence precede the elements of said second address subsequence; g. storing the next higher keyfield bit of each of said keyfields in the same holding register storage locations which held the low order keyfield bit of the same keyfield; h. interrogating each of said next higher keyfield bits in a sequence controlled by said second address sequence; i. processing said second address sequence under control of said sequentially interrogated next higher keyfield bits to provide a third address subsequence including all addresses accessing record units whose said next higher keyfield bit is a ''''0'''' and a fourth address subsequence including all addresses accessing record units whose said next higher keyfield bit is a ''''1''''; j. combining said third and fourth address subsequences to form a third address sequence wherein the elements of said third address subsequence precede the elements of said fourth address subsequence; k. repeating said steps of storing the next higher keyfield bits, interrogating them in a sequence controlled by the previously combined address sequence and processing said previously combined address sequence under transfer control of said sequentially interrogated keyfield bits to form two new address subsequences which are then Combined to form a new address sequence, until the high order keyfield bit of each of said record units has been interrogated and a final address sequence has been produced; l. selectively transferring said record units from a first random access storage to a second data storage in an access sequence controlled by said final address sequence, whereby said record units are stored on said second data storage in sequence of ascending keyfield value.
Claim 43
Dependent Claim
71 words
The method of claim 36 wherein the step of processing a previously combined address sequence to form two new address subsequences is accomplished by transferring an address of said sequence to consecutively addressable storage locations within a first storage area if the associated keyfield bit being interrogated is a ''''0'''' and to consecutively addressable storage locations within a second storage area if the associated keyfield bit being interrogated is a ''''1''''.
Claim 44
Dependent Claim
38 words
The method of claim 37 wherein the step of combining said address subsequences to form a new address sequence is accomplished by consecutively reading out the contents of said first storage area followed by said second storage area.
Claim 45
Dependent Claim
65 words
The method of claim 38 wherein said new address sequence is processed to form two subsequences by transferring particular elements of said new sequence to consecutive storage locations within a third storage area if the associated keyfield bit being then interrogated is a ''''0'''' and to consecutive storage locations within a fourth storage area if the associated keyfield bit being then interrogated is a ''''1''''.
Claim 46
Dependent Claim
70 words
The method of claim 39 wherein address sequence elements are repeatedly transferred between said first and second storage areas on the one hand and said third and fourth storage areas on the other hand under control of the values of successively higher corresponding keyfield bits until the highest order bit of each keyfield has been interrogated and a final combined address sequence is formed on the basis of said interrogation.
Claim 47
Dependent Claim
78 words
The method of claim 40 wherein the step of selectively transferring said record units from said random access storage to said data storage further comprises the steps of successively storing the bits of corresponding position from each of said record units in the same holding register storage locations in which the associated keyfield bits were held and selectively accessing said storage locations for readout to said second data storage in a sequence controlled by said final address sequence.
Claim 48
Dependent Claim
66 words
The method of claim 41 wherein said record units are initially stored in a cyclic magnetic storage in sequential order and non-interlaced format and wherein keyfield bits of corresponding significance are stored in said holding register storage locations by sequential transfer of said bits from said cyclic storage to a serial to parallel converter whose outputs are connected in parallel to said holding register storage locations.
Claim 49
Dependent Claim
57 words
The method of claim 41 wherein said record units are initially stored in a cyclic magnetic storage in interlaced format and wherein keyfield bits of corresponding significance are stored in said holding register storage locations by parallel transfer of said bits from said cyclic storage through a plurality of spaced transducing means associated with said cyclic storage.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-30 | 1976-07-31 | 1977-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-30 | 1980-07-31 | 1981-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-30 | 1984-07-31 | 1985-01-30 | $7700.00 | Window Closed / Lapsed |