US3714602A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Amplifier circuit having a controllable gain
Assignee: SERVO CORP
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Filing: 1970-11-12
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Granted: 1973-01-30
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Expires: 1990-11-12
Abstract
Abstract A signal amplifying circuit including an operational amplifier and a single field effect transistor for controlling the gain of the operational amplifier while producing minimal DC offset voltage at the output of the operational amplifier. The operational amplifier is capable of producing amplified output signals from dc to the megahertz range.
Inventors
- 👤 F Macey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:15
CPC Classifications
H; H03; H03K; H03K7/00; H03K7/02; H03G; H03G3/00; H03G3/02; H03G3/04; H03G3/10; H03G3/12
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
413 words
An amplifier circuit having a controllable gain, comprising: an input signal terminal adapted to receive an input signal to be amplified, said signal including an initial DC component; linear differential amplifier means having a first input terminal, a second input terminal and an output terminal; coupling means for coupling an input signal at the input signal terminal to the first input terminal of the linear differential amplifier means; feedback means including a pair of series-connected resistances connected between the output terminal and the input terminal of the linear differential amplifier means for providing a feedback voltage between the output terminal and the input terminal of the linear differential amplifier means; a control input terminal adapted to receive a control signal condition; a field effect transistor having a first electrode connected to the juncture of the pair of series-connected resistances, a second electrode, and a third electrode; bias means coupled to the control input terminal and to the second electrode of the field effect transistor for establishing a bias voltage between the second and third electrodes of the field effect transistor which is sufficient to cause the field effect transistor to operate in the linear range of the resistance characteristic curve of resistance between the first and third electrodes of the field effect transistor when a control signal condition is at the control input terminal; said field effect transistor being operative when a control signal condition is at the control input terminal to change the value of the voltage at the juncture of the pair of seriesconnected resistances thereby to change the value of the feedback voltage between the output terminal and the input terminal of the linear differential amplifier means; said linear differential amplifier means being operative when the feedback voltage between its output terminal and its input terminal is changed by the field effect transistor and when an input signal is at its input terminal to produce an output signal at its output terminal amplified by a value of gain determined by the amount of change in the value of the feedback voltage between its output and input terminals; a source of reference potential; and means coupled to the second input terminal of the linear differential amplifier means and to the source of reference potential for preventing the occurrence of an initial DC offset voltage at the output terminal of the linear differential amplifier means when an input signal having an initial DC component is present at the first-mentioned input terminal thereof.
Claim 2
Dependent Claim
413 words
An amplifier circuit having a controllable gain, comprising: an input signal terminal adapted to receive an input signal to be amplified, said signal including an initial DC component; linear differential amplifier means having a first input terminal, a second input terminal and an output terminal; coupling means for coupling an input signal at the input signal terminal to the first input terminal of the linear differential amplifier means; feedback means including a pair of series-connected resistances connected between the output terminal and the input terminal of the linear differential amplifier means for providing a feedback voltage between the output terminal and the input terminal of the linear differential amplifier means; a control input terminal adapted to receive a control signal condition; a field effect transistor having a first electrode connected to the juncture of the pair of series-connected resistances, a second electrode, and a third electrode; bias means coupled to the control input terminal and to the second electrode of the field effect transistor for establishing a bias voltage between the second and third electrodes of the field effect transistor which is sufficient to cause the field effect transistor to operate in the linear range of the resistance characteristic curve of resistance between the first and third electrodes of the field effect transistor when a control signal condition is at the control input terminal; said field effect transistor being operative when a control signal condition is at the control input terminal to change the value of the voltage at the juncture of the pair of seriesconnected resistances thereby to change the value of the feedback voltage between the output terminal and the input terminal of the linear differential amplifier means; said linear differential amplifier means being operative when the feedback voltage between its output terminal and its input terminal is changed by the field effect transistor and when an input signal is at its input terminal to produce an output signal at its output terminal amplified by a value of gain determined by the amount of change in the value of the feedback voltage between its output and input terminals; a source of reference potential; and means coupled to the second input terminal of the linear differential amplifier means and to the source of reference potential for preventing the occurrence of an initial DC offset voltage at the output terminal of the linear differential amplifier means when an input signal having an initial DC component is present at the first-mentioned input terminal thereof.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-30 | 1976-07-31 | 1977-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-30 | 1980-07-31 | 1981-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-30 | 1984-07-31 | 1985-01-30 | $7700.00 | Window Closed / Lapsed |