Abstract A decoder is disclosed for a binary bit stream in which a transition occurs at the middle of a bit cell containing a ''''1,'''' and a transition occurs at the partition between adjacent bit cells containing ''''0''s.'''' A reference wave derived from the bit stream and having a period equal to a bit-cell width, and the binary bit stream, are applied to a multiplier to produce a product wave. The product wave is translated by integrate-anddump circuits, or by a low-pass filter, to a modified product wave in which low-frequency components are predominant. A first comparator means produces a ''''1'''' output when the portion of the modified product wave corresponding to a bit cell is more positive or more negative than the portions of the modified product wave corresponding to both the preceding and following bit cells. A second comparator means produces a ''''1'''' output when the portion of the modified product wave corresponding to a bit cell has a larger absolute value than the portion of the modified product wave corresponding to the unit preceding the center of the bit cell and the unit following the center of the bit cell.
A decoder responsive to a binary bit stream in which a transition occurs at the middle of a bit cell containing a ''''1,'''' and a transition occurs at the partition between adjacent bit cells containing ''''0''s,'''' and a reference square wave, having a period equal to a bit-cell width, derived from said binary bit stream, comprising means to multiply the binary bit stream and the reference square wave to produce a product wave, a low-pass filter receptive to said product wave and producing a filtered output wave, means to sample the filtered wave at the center of a bit cell and the centers of preceding and following bit cells, and to produce an output when there is a voltage difference of the same polarity between the center of a bit cell and the centers of preceding and following bit cells, means to full-wave rectify the filtered output wave, means to sample the rectified wave at the center and at both edges of a bit cell, and to produce an output when there is a voltage difference between the center of a bit cell and each of the two edges of the bit cell, and means to combine the outputs produced by said two means to sample the filtered wave to produce a ''''1'''' output signal.
Claim 2
Dependent Claim
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A decoder responsive to a binary bit stream in which a transition occurs at the middle of a bit cell containing a ''''1,'''' and a transition occurs at the partition between adjacent bit cells containing ''''0''s,'''' and a reference square wave, having a period equal to a bit-cell width, derived from said binary bit stream, comprising means to multiply the binary bit stream and the reference square wave to produce a product wave, a low-pass filter receptive to said product wave and producing a filtered output wave, means to sample the filtered wave at the center of a bit cell and the centers of preceding and following bit cells, and to produce an output when there is a voltage difference of the same polarity between the center of a bit cell and the centers of preceding and following bit cells, means to full-wave rectify the filtered output wave, means to sample the rectified wave at the center and at both edges of a bit cell, and to produce an output when there is a voltage difference between the center of a bit cell and each of the two edges of the bit cell, and means to combine the outputs produced by said two means to sample the filtered wave to produce a ''''1'''' output signal.