Digital to analog converter

Claim 2

A digital-to-analog converter comprising, in combination, a digital binary counter adapted to count input pulses thereto in a forward direction between a predetermined lower limit and a predetermined upper count limit when an up signal is applied thereto and to count backwards between said limits when a down signal is applied thereto, means for generating one quadrant of a staircase voltage wave in which each step is a function of a discrete count stored in said counter each time said counter proceeds between said upper and lower limits, means operable after said counter is at said upper limit for applying said down signal to said counter and also operable after said counter is at said lower limit for applying said up signal to said counter, and means operable each time said counter reaches said lower limit to reverse the polarity of said voltage steps derived by said generating means to thereby form successive half cycles of opposite polarity of said staircase wave.

Claim 3

A digital-to-analog converter in accordance with claim 1 wherein said means for applying said up and down signals includes first detecting means for sensing when said counter is at said lower limit count, second detecting means for sensing when said counter is at said upper limit count, and means operable after the output of said first and said second detecting means respectively for applying said up signal and said down signal to said counter.

Claim 4

A digital-to-analog converter in accordance with claim 1 wherein said counter is set to said lower limit when a clear input signal is applied thereto, and including first detecting means for sensing when said counter is at said lower limit count, and holding means operable subsequent to the output of said first detecting means for temporarily applying said clear input signal to said counter.

Claim 5

A digital-to-analog converter in accordance with claim 3 wherein said holding means includes first flip-flop means responsive to both the output of said first detecting means and to the trailing edge of the pulse which set said counter to said lower limit count for applying said clear input signal to said counter and being responsive to the trailing edge of the succeeding input pulse to remove said clear signal.

Claim 6

A digital-to-analog converter in accordance with claim 3 wherein said means to reverse the polarity of said staircase wave voltage steps includes inverting means operable between first and second states in which said voltage steps are inverted and are not inverted respectively, and quadrant control means operable after successive outputs from said holding means to alternately operate said inverting means between said first and second states.

Claim 7

A digital-to-analog converter in accordance with Claim 4 wherein said means to reverse the polarity of said staircase wave voltage steps includes inverting means operable between first and second states in which said voltage steps are inverted and are not inverted respectively, and quadrant control means responsive to both an output from said first flip-flop means and said succeeding pulse to operate said inverting means to said first state and also being responsive to both a succeeding like output from said first flip-flop means and said succeeding pulse to operate said inverting means to said second state.

Claim 8

A digital-to-analog converter in accordance with claim 6 wherein said inverting means includes an operational amplifier having inverting and non-inverting inputs and equal minus and plus gain for signals coupled respectively thereto and switching means responsive to logic 1 and logic 0 inputs respectively to couple said voltage steps alternately to said inverting and non-inverting inputs of said amplifier, and wherein said quadrant control means includes NAND gate means for providing a logic 0 output in response to both an output from said first flip-flop means and said succeeding pulse and means including second flip-flop means resPonsive to successive logic 0 outputs from said NAND gate means to alternately apply said logic 0 and logic 1 signals to said switching means.

Claim 9

A digital-to-analog converter in accordance with claim 1 and including means to temporarily block change of the count stored in said counter while said up and down signals are being switched.

Claim 10

A digital-to-analog converter in accordance with claim 1 wherein the magnitude of each of said staircase wave voltage steps is approximately equal to the sine of the ratio of stored count/ upper limit count times 90* times the peak voltage of said staircase wave, and also including means for generating one quadrant of a cosine voltage staircase wave in which each step is a cosine function of each discrete count stored in said counter each time said counter proceeds between said upper and lower limits, the magnitude of each voltage step of said staircase cosine wave being approximately equal to the cosine of the ratio of stored count/ upper limit count times 90* times the peak voltage of said staircase cosine wave, and means operable after each time said counter reaches said upper limit count to reverse the polarity of said voltage steps of said cosine staircase wave to thereby form successive half cycles of opposite polarity of said cosine wave.

Claim 11

A digital-to-analog converter in accordance with claim 9 and including magnitude control means for selectively varying the magnitude of said steps of said sine and of said cosine staircase waves by the same factor.

Claim 12

A digital-to-analog converter in accordance with claim 4 and including means for selectively reversing said up and down signal applying means to remove the signal then being applied to said counter and to apply the opposite signal thereto and thereby reverse the direction of counting by said counter and the sequence in which the quadrants of said sine and cosine waves are being generated.

Claim 13

A digital-to-analog converter in accordance with claim 2 wherein said means to reverse the polarity of said voltage steps includes, means for amplifying said voltage steps of said staircase wave and being adapted to invert said voltage steps in response to an inverting input signal, and means operable after successive outputs from said first detecting means to alternately apply said inverting signal to and to remove said inverting signal from said amplifying means.

Claim 14

A digital-to-analog converter in accordance with claim 1 wherein the magnitude of each of said voltage steps is approximately equal to the sine of the ratio of stored count/upper limit count times 90* times the peak voltage of said staircase wave, said counter includes a plurality of cascaded flip-flops, and said means for generating said steps of said staircase voltage wave includes a plurality of parallel branch circuits each of which includes the series arrangement of a resistor and the emitter-collector circuit of a transistor having its base coupled to the output of one of said flip-flops of said counter and also includes a voltage drop resistor in series with said parallel branch circuits.

Claim 15

A digital-to-analog converter in accordance with claim 13 wherein said means for reversing the polarity of said staircase wave voltage steps includes an amplifier having inverting and non-inverting inputs, transistor switching means for coupling said voltage drop resistor alternately to said inverting and non-inverting inputs in response to logic 0 and logic 1 input signals, first detecting means for sensing when said counter is at said lower limit count, and quadrant control means operable after successive outputs from said first detecting means for alternately applying logic 1 and logic 0 signals to said transistor switching means.

Claim 16

A digital-to-analog converter in accordance with claim 2 wherein said counter includes a plurality of cascaded flip-flops having Q and Q outputs, said first detecting means includes a first NAND gate Having its inputs individually coupled to the Q outputs of said flip-flops, and said second detecting means includes a second NAND gate having its inputs individually coupled to the Q outputs of each flip-flop.

Claim 17

A digital-to-analog converter in accordance with claim 15 wherein said means for applying said up and down signals includes first gate means for deriving logic 0 and logic 1 signals respectively in response to the logic 0 output from said first and second NAND gates, and up/down circuit means responsive to said logic 0 and logic 1 signals respectively from said first gate means for applying said up and down signals to said counter.

Claim 18

A digital-to-analog converter in accordance with claim 16 wherein said counter is prevented from changing the count stored therein when a blocking signal is applied thereto, and said up/down circuit means includes means responsive to said logic 0 signal or to said logic 1 signal from said first gate means to apply a blocking signal to said counter and to subsequently derive a delay signal after a predetermined time delay, means responsive to both said logic 0 signal from said first gate means and said delay signal to apply said up signal to said counter and also being responsive to both said logic 1 signal from said first gate means and said delay signal to apply said down signal to said counter, said blocking signal applying means being adapted to remove said blocking signal subsequent to each operation of said last-named means.

Claim 19

A digital-to-analog converter in accordance with claim 16 wherein said first gate means includes third and fourth NAND gates having one input coupled to the output of said first and second NAND gates respectively, the output of said third NAND gate being coupled to another input to said fourth NAND gate.

Claim 20

A digital-to-analog converter in accordance with claim 18 having means including gate means operable after the outputs from said first and second detecting means respectively for applying logic 0 and logic 1 signals to the other input to said third NAND gate so that the inputs to said third NAND gate agree when said counter is at said lower limit and the inputs to said fourth NAND gate agree when said counter is at said upper limit and the logic 1 or logic 0 output from said first gate means remains the same after said counter has counted away from either of said limits.

Claim 21

A digital-to-analog converter in accordance with claim 19 and including means for selectively reversing the signal on said other input of said third NAND gate between logic 1 and logic 0 to thereby change the output of said first gate means between logic 1 and logic 0 and thus effect a change in the direction of counting by said counter.

Claim 22

A digital-to-analog converter in accordance with claim 9 wherein said counter is set to said lower and upper limit counts when clear and preset signals respectively are applied thereto, and said converter includes, first and second detecting means for sensing when said counter is at said lower and upper limits respectively, and first and second holding means operable subsequent to the outputs of said first and second detecting means respectively for temporarily applying said clear and preset signals to said counter.

Claim 23

A digital-to-analog converter in accordance with claim 21 wherein said first holding means includes first flip-flop means responsive to both the output of said first detecting means and the trailing edge of the pulse which set said counter to said lower limit for applying said clear signal to said counter and being responsive to the trailing edge of the succeeding pulse to remove said clear signal, and said second holding means includes second flip-flop means responsive to both the output of said second detecting means and the trailing edge of the pulse which set said counter to said upper limit for applying said preset signal to said couNter and being responsive to the trailing edge of the succeeding pulse to remove said preset signal.

Claim 24

A digital-to-analog converter in accordance with claim 22 wherein said means to reverse the polarity of said staircase sine wave voltage steps includes first inverting means operable between first and second states in which said voltage steps are inverted and are not inverted respectively and first switching means responsive to logic 1 and logic 0 input signals to operate said first inverting means between said first and second states alternately, said means to reverse the polarity of said cosine staircase wave voltage steps includes second inverting means operable between first and second states in which said voltage steps are inverted and are not inverted respectively and second switching means responsive to logic 1 and logic 0 input signals to operate said second inverting means between said first and second states alternately, and quadrant control means for applying logic 1 and logic 0 input signals to said first and second switching means and being indexed after each operation of said first holding means to reverse the input signals to said first switching means and also being indexed after each operation of said second holding means to reverse the input signals to said second switching means.

Claim 25

A digital-to-analog converter in accordance with claim 23 and including means for selectively reversing the input signals to said first and second switching means to thereby invert the voltage steps of said sine and cosine staircase waves.

Claim 26

A digital-to-analog converter in accordance with claim 23 wherein said quadrant control means is indexed to reverse said input signals to said first switching means between logic 1 and logic 0 in response to both each output of said first holding means and a succeeding input pulse to said counter and is indexed to reverse said input signals to said second switching means between logic 1 and logic 0 in response to both each output of said second holding means and a succeeding input pulse to said counter.

Claim 27

A digital-to-analog converter in accordance with claim 25 wherein said quadrant control means includes fifth and sixth NAND gates each of which receives the input pulses to said counter on one input thereof, a second input of said fifth NAND gate being coupled to an output of said first holding means, and a second input of said sixth NAND gate being coupled to an output of said second holding means.

Claim 28

A digital-to-analog converter in accordance with claim 26 wherein said quadrant control means includes third and fourth flip-flops having Q outputs on which said logic input signals to said first and second switching means respectively are generated, said third and fourth flip-flops having data inputs and being adapted upon receipt of a triggering pulse to transfer the information on said data input to said Q output, means responsive to logic 0 outputs from said fifth and sixth NAND gates respectively for applying triggering signals to said third and fourth flip-flops, and means for supplying logic 1 and logic 0 signals alternately to said data inputs of said third and of said fourth flip-flops to reverse the logic input signal on the data input of the other flip-flop.

Claim 29

A digital-to-analog converter in accordance with claim 27 wherein said fourth flip-flop has Q and Q outputs, said means to reverse the logic signal on said data inputs includes first and second exclusive OR gates each of which has an input connected to a quadrant sequence control bus, a second input of said first exclusive OR gate being coupled to the Q output of said third flip-flop and the output of said first exclusive OR gate being coupled to the data input of said fourth flip-flop, a second input of said second exclusive OR gate being coupled to the Q output of said fourth flip-flop and the output of said second exclusive OR gate being coupleD to the data input of said third flip-flop, whereby selective reversal of the signal on said quadrant sequence control bus reverses the sequence in which the quadrants of said sine and cosine staircase waves are generated.

Claim 30

A digital-to-analog converter comprising, in combination, digital binary counter means for counting input pulses thereto in a forward direction between a predetermined lower limit and a predetermined upper limit count when an up signal is applied thereto and for counting backwards between said limits when a down signal is applied thereto, means for generating one quadrant of a sine voltage staircase wave in which each step is a sine function of a discrete count stored in said counter means each time said counter means proceeds between said upper and lower limits, means for generating one quadrant of a cosine voltage staircase wave on which each step is a cosine function of discrete count stored in said counter means each time said counter means proceeds between said upper and lower limits, first detecting means for sensing when said counter means is at said lower limit, second detecting means for sensing when said counter means stores said upper limit count, means operable after each output from said first detecting means to apply said up signal to said counter means and operable after each output from said second detecting means to apply said down signal to said counter means, means operable after each output from said first detecting means for reversing the polarity of said voltage steps of said sine staircase wave to thereby form successive half cycles of opposite polarity of said sine staircase wave, and means operable after each output from said second detecting means for reversing the polarity of said voltage steps of said cosine staircase wave to thereby form successive half cycles of opposite polarity of said cosine staircase wave.

Claim 31

A digital-to-analog converter comprising, in combination, digital binary counter means for counting input pulses thereto in a forward direction between a predetermined lower limit and a predetermined upper limit count when an up signal is applied thereto and for counting backwards between said limits when a down signal is applied thereto, means for generating one quadrant of a sine voltage staircase wave in which each step is a sine function of a discrete count stored in said counter means each time said counter means proceeds between said upper and lower limits, means for generating one quadrant of a cosine voltage staircase wave on which each step is a cosine function of discrete count stored in said counter means each time said counter means proceeds between said upper and lower limits, first detecting means for sensing when said counter means is at said lower limit, second detecting means for sensing when said counter means stores said upper limit count, means operable after each output from said first detecting means to apply said up signal to said counter means and operable after each output from said second detecting means to apply said down signal to said counter means, means operable after each output from said first detecting means for reversing the polarity of said voltage steps of said sine staircase wave to thereby form successive half cycles of opposite polarity of said sine staircase wave, and means operable after each output from said second detecting means for reversing the polarity of said voltage steps of said cosine staircase wave to thereby form successive half cycles of opposite polarity of said cosine staircase wave.

Claim 32

A digital-to-analog converter in accordance with claim 29 and including magnitude control means for selectively varying the magnitude of said voltage steps of said sine and cosine staircase waves by the same factor.

Claim 33

A digital-to-analog converter in accordance with claim 29 wherein said means for reversing the polarity of said sine wave voltage steps include first inverting means for said voltage steps operable between first and second states in which said voltage steps are inverted and are not inverted respectively and first switching means for alternately operating said first inverting means between said first and second states in response to logic 0 and logic 1 input signals, said means for reversing the polarity of said cosine wave voltage steps include second inverting means for said voltage steps operable between first and second states in which said voltage steps are inverted and are not inverted respectively and second switching means for alternately operating said second inverting means between said first and second states in response to logic 0 and logic 1 input signals, and wherein said converter includes quadrant control means for applying logic 1 and logic 0 input signals to said first switching means alternately after successive outputs from said first detecting means and for applying logic 1 and logic 0 input signals alternately to said second switching means after successive outputs from said second detecting means.

Claim 34

A digital-to-analog converter in accordance with claim 31 wherein said counter means is adapted to store said lower and upper limit counts respectively when clear and preset signals are applied thereto, and wherein said converter includes first holding means operable after each output from said first detecting means for applying said clear signal to said counter means, and second holding means operable after each output from said second detecting means for applying said preset signal to said counter means.

Claim 35

A digital-to-analog converter in accordance witH claim 32 wherein said first holding means is responsive to both the output from said first detecting means and the trailing edge of the input pulse which set said counter means at said lower limit count and said second holding means is responsive to both the output from said second detecting means and the trailing edge of the pulse which switched said counter means to said upper limit count.

Claim 36

A digital-to-analog converter in accordance with claim 33 wherein said quadrant control means is responsive to both each output from said first holding means and a succeeding input pulse to reverse said logic 1 and logic 0 input signals to said first switching means and is also responsive to both each output from said second holding means and a succeeding input pulse to reverse said logic 1 and logic 0 input signals to said second switching means.

Claim 37

A digital-to-analog converter in accordance with claim 34 wherein said first holding means is responsive to the trailing edge of said succeeding pulse to remove said clear signal, and said second holding means is responsive to the trailing edge of said succeeding pulse to remove said preset signal.

Claim 38

A digital-to-analog converter in accordance with claim 35 wherein said quadrant control means includes first and second NAND gates each of which receives said input pulses on one input thereof, a second input of said first NAND gate being coupled to an output of said first holding means and a second input of said second NAND gate being coupled to an output of said second holding means.

Claim 39

A digital-to-analog converter in accordance with claim 36 wherein said quadrant control means includes first and second flip-flop means having Q outputs on which said logic input signals to said first and second switching means respectively are derived, said first and second flip-flop means having data inputs and being adapted upon receipt of a triggering signal to transfer the information on said data input to said Q output, means responsive to logic 0 outputs from said first and second NAND gates respectively for applying triggering signals to said first and second flip-flop means, and means for supplying logic 1 and logic 0 signals alternately to said data inputs of said first and second flip-flop means and being responsive to the reversal of the output of either of said flip-flop means to reverse the logic input signal on said data input of said other flip-flop means.

Claim 40

A digital-to-analog converter in accordance with claim 37 wherein said second flip-flop means has Q and Q outputs, said means to reverse the signal on said data input of said first and second flip-flop means includes first and second exclusive OR gates each of which has an input connected to a quadrant sequence control bus, a second input of said second exclusive OR gate being coupled to the Q output of said second flip-flop means and the output of said second exclusive OR gate being coupled to the data input of said first flip-flop means, a second input of said first exclusive OR gate being coupled to the Q output of said first flip-flop means and the output of said first exclusive OR gate being coupled to the data input of said second flip-flop means.

Claim 41

A digital-to-analog converter in accordance with claim 38 wherein said counter means has a plurality of cascaded flip-flops having Q and Q outputs, said first detecting means includes a third NAND gate having inputs coupled individually to the Q outputs of said flip-flops of said counter means and said second detecting means includes a fourth NAND gate having inputs individually coupled to the Q outputs of said flip-flops of said counter means.

Claim 42

A digital-to-analog converter in accordance with claim 38 wherein said up and down signal applying means includes fifth and sixth NAND gates having one input respectively coupled to the output of said third and fourth NAND gates, the output of said fifth NAND gate being coupled to a second input of said sixth NAND gate, a third exclusive OR gate having inputs connected to the outputs of said first and second exclusive OR gates, and a fourth exclusive OR gate having a first input coupled to said quadrant sequence control bus and a second input coupled to the output of said third exclusive OR gate and its output coupled to another input of said fifth NAND gate.

Claim 43

A digital-to-analog converter in accordance with claim 39 wherein said up and down signal applying means includes NAND gate means coupled to the outputs of said third and fourth NAND gates for providing logic 0 and logic 1 signals respectively in response to logic 0 outputs from said third and fourth NAND gates.

Claim 44

A digital-to-analog converter in accordance with claim 41 wherein said counter means includes gate means for blocking change of the count stored in said counter when a blocking signal is applied thereto, and said up and down signal applying means includes means responsive to said logic 1 or said logic 0 output from said NAND gate means to apply a blocking signal to said counter and to subsequently provide a delay signal after a preselected time interval, means responsive to both said logic 1 output from said NAND gate means and said delay signal to apply said down signal to said counter and also being responsive to both said logic 0 output from said NAND gate means and said delay signal to apply said up signal to said counter, and means for removing said blocking signal after application of said up signal or said down signal to said counter by said last-named means.

Claim 45

A digital-to-analog converter in accordance with claim 40 wherein said up and down signal applying means includes fifth and sixth NAND gates having one input coupled respectively to the output of said third and fourth NAND gates, the output of said fifth NAND gate being coupled to a second input to said sixth NAND gate, and gate means responsive to each output of said first flip-flop means of said quadrant control means for applying a logic 0 signal to a second input to said fifth NAND gate so that the inputs thereto agree and also being responsive to each output of said second flip-flop means of said quadrant control means for applying a logic 1 signal to said second input of said fifth NAND gate so that the inputs to said sixth NAND gate agree and said up and down signal applying means do not switch when said counter proceeds away from said lower or said upper limit count.

Claim 46

A digital-to-analog converter in accordance with claim 31 wherein said counter means has a plurality of cascaded flip-flops having Q and Q outputs and said means for generating said staircase sine voltage wave includes a plurality of parallel branches each of which includes the series arrangement of a resistor and the emitter-collector circuit of a transistor having its base coupled to the Q output of one of said flip-flops and a first voltage drop resistor in series with said parallel branches, and said means for generating said staircase wave cosine voltage includes a plurality of parallel branches each of which includes the series arrangement of a resistor and the emitter-collector circuit of a transistor having its base coupled to the Q output of one of said flip-flops and a second voltage drop resistor in series with said parallel branches.

Claim 47

A digital-to-analog converter in accordance with claim 44 wherein said first inverting means includes a first operational amplifier having inverting and non-inverting inputs and equal minus and plus gain for signals coupled respectively thereto and said first switching means couples said first voltage drop resistor alternately to said inverting and non-inverting inputs of said first amplifier and said second inverting means includes a second operational amplifier having inverting and non-inverting and equal minus and plus gain for signals coupled respectively thereto and said seCond switching means couples said second voltage drop resistor alternately to said inverting and non-inverting inputs of said second amplifier.

Claim 48

A digital-to-analog converter in accordance with claim 41 wherein said counter means includes gate means for preventing change of the count stored therein when a blocking signal is applied thereto, said up and down signal applying means includes first bistable latch means operable to first and second conditions respectively to apply said blocking signal to and to remove it from said counter means, and means including a fifth exclusive OR gate responsive to the change of the output signal from said NAND gate means to either logic 1 or logic 0 for switching said first bistable latch means to said first condition to apply said blocking signal to said counter means.

Claim 49

A digital-to-analog converter in accordance with claim 46 wherein said up and down signal applying means also includes second bistable latch means having an input coupled to the output of said NAND gate means, a clock input, and a first output of which said up and down signals are generated and being adapted to change states and reverse the signals on said first output in response to both changes of said logic 1 and logic 0 signals from said NAND gate means and a triggering signal on said clock input, and means responsive to switching of said first bistable latch means to said first condition to apply a triggering signal to said clock input of said second bistable latch means after a predetermined time delay.

Claim 50

A digital-to-analog converter in accordance with claim 47 wherein said second bistable latch means has a second output coupled to an input of said fifth exclusive OR gate, and said means for switching said first bistable latch means is responsive to the reversal of the output of said fifth exclusive OR gate to switch said first bistable latch means to said second condition and thereby remove said blocking signal after change of states of said second bistable latch means to reverse said up and down signals.

Claim 51

A digital-to-analog converter in accordance with claim 41 wherein said counter means includes gate means for preventing change of the count stored therein when a blocking signal is applied thereto, said up and down signal applying means includes a fifth exclusive OR gate having an input connected to the output of said NAND gate means, first bistable latch means having a data input coupled to the output of said fifth exclusive OR gate, a clock input, a Q output, and a Q output on which said blocking signal is derived and being adapted to transfer the information on said data input to its Q output and apply the opposite logic signal to its Q output when a triggering signal is applied to said clock input, and clock signal deriving means for applying a triggering signal to said clock input of said first bistable latch means in response to both a logic 1 output from said fifth exclusive OR gate and logic 0 on said Q output of said first bistable latch means and also in response to both logic 0 output from said fifth exclusive OR gate and logic 1 on said Q output of said first bistable latch means.

Claim 52

A digital-to-analog converter in accordance with claim 49 wherein said means for applying said up and down signals also includes second bistable latch means having a data input coupled to the output of said NAND gate means, a clock input, a Q output on which said up and down signals are derived, and a Q output coupled to another input of said fifth exclusive OR gate and being adapted to transfer the information on said data input to its Q output and apply the opposite logic signal to its Q output when a triggering sign is applied to said data input, and time delay means responsive to logic 1 on said Q output of first bistable latch means for applying a triggering signal to said clock input of said second bistable latch means after a predetermined time dElay and thereby reverse said up and down signals applied to said counter means and also the logic signal on said another input to said fifth exclusive OR gate.